Datasheet
© 2009 Microchip Technology Inc. DS39663F-page 127
PIC18F87J10 FAMILY
TABLE 11-3: PORTA FUNCTIONS
TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input.
1 I TTL PORTA<0> data input; disabled when analog input enabled.
AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input.
1 I TTL PORTA<1> data input; disabled when analog input enabled.
AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
RA2/AN2/V
REF-RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when
CV
REF output enabled.
1 I TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
REF output enabled.
AN2 1 I ANA A/D Input Channel 2 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
V
REF- 1 I ANA A/D and Comparator low reference voltage input.
RA3/AN3/V
REF+RA3 0 O DIG LATA<3> data output; not affected by analog input.
1 I TTL PORTA<3> data input; disabled when analog input enabled.
AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR.
V
REF+ 1 I ANA A/D high reference voltage input.
RA4/T0CKI RA4 0 O DIG LATA<4> data output.
1 I ST PORTA<4> data input; default configuration on POR.
T0CKI x I ST Timer0 clock input.
RA5/AN4 RA5 0 O DIG LATA<5> data output; not affected by analog input.
1 I TTL PORTA<5> data input; disabled when analog input enabled.
AN4 1 I ANA A/D Input Channel 4. Default configuration on POR.
Legend: PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTA
— — RA5 RA4 RA3 RA2 RA1 RA0 56
LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 56
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.