Datasheet

PIC18F87J10 FAMILY
DS39663F-page 76 © 2009 Microchip Technology Inc.
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 56, 243
BAUDCON1 ABDOVF RCIDL
— SCKP BRG16 — WUE ABDEN 01-0 0-00 56, 242
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 56, 243
BAUDCON2 ABDOVF RCIDL
— SCKP BRG16 — WUE ABDEN 01-0 0-00 56, 242
ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 57, 188
TMR4 Timer4 Register 0000 0000 57, 168
PR4 Timer4 Period Register 1111 1111 57, 168
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 57, 167
CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 57, 170
CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 57, 170
CCP4CON
— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 57, 169
CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 57, 170
CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 57, 170
CCP5CON
— — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 57, 169
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 57, 243
RCREG2 EUSART2 Receive Register 0000 0000 57, 251,
252
TXREG2 EUSART2 Transmit Register 0000 0000 57, 249,
250
TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 57, 240
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 57, 241
ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 57, 189
ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 57, 188
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 57, 189
ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 57, 188
SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 57, 203,
238
SSP2ADD MSSP2 Address Register (I
2
C™ Slave mode), MSSP2 Baud Rate Reload Register (I
2
C Master mode) 0000 0000 57, 203
SSP2STAT SMP CKE D/A
PSR/WUA BF 0000 0000 57, 194,
204
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 57, 206,
205
SSP2CON2 GCEN ACKSTAT ACKDT/
ADMSK5
ACKEN/
ADMSK4
RCEN/
ADMSK3
PEN/
ADMSK2
RSEN/
ADMSK1
SEN 0000 0000 57, 206
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Serial Programming modes.
2: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
3: This register and its bits are not implemented in 64-pin devices. In 80-pin devices, the bits are unwritable and read as ‘0’ in Microcontroller
mode.
4: The PLLEN bit is available only when either ECPLL or HSPLL Oscillator modes are selected; otherwise, the bit is read as ‘0’.
5: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.