Datasheet

PIC18F87J10 FAMILY
DS39663F-page 402 © 2009 Microchip Technology Inc.
RCON Register
Bit Status During Initialization ....................................52
Reader Response ............................................................ 406
Register File ....................................................................... 71
Register File Summary ................................................. 73–76
Registers
ADCON0 (A/D Control 0) .........................................261
ADCON1 (A/D Control 1) .........................................262
ADCON2 (A/D Control 2) .........................................263
BAUDCONx (Baud Rate Control) ............................242
CCPxCON (CCPx Control) ......................................169
CCPxCON (ECCPx Control) .................................... 177
CMCON (Comparator Control) ................................ 271
CONFIG1H (Configuration 1 High) .......................... 283
CONFIG1L (Configuration 1 Low) ............................ 283
CONFIG2H (Configuration 2 High) .......................... 284
CONFIG2L (Configuration 2 Low) ............................ 284
CONFIG3H (Configuration 3 High) .......................... 285
CONFIG3L (Configuration 3 Low) ...................... 61, 285
CVRCON (Comparator Voltage
Reference Control) ........................................... 277
DEVID1 (Device ID 1) .............................................. 286
DEVID2 (Device ID 2) .............................................. 286
ECCPxAS (Enhanced CCPx Auto-Shutdown
Control) ............................................................ 189
ECCPxDEL (PWM Dead-Band Delay) ..................... 188
EECON1 (EEPROM Control 1) .................................. 87
INTCON (Interrupt Control) ......................................111
INTCON2 (Interrupt Control 2) ................................. 112
INTCON3 (Interrupt Control 3) ................................. 113
IPR1 (Peripheral Interrupt Priority 1) ........................ 120
IPR2 (Peripheral Interrupt Priority 2) ........................ 121
IPR3 (Peripheral Interrupt Priority 3) ........................ 122
MEMCON (External Memory Bus Control) ................ 96
OSCCON (Oscillator Control) .................................... 36
OSCTUNE (PLL Control) ........................................... 33
PIE1 (Peripheral Interrupt Enable 1) ........................ 117
PIE2 (Peripheral Interrupt Enable 2) ........................ 118
PIE3 (Peripheral Interrupt Enable 3) ........................ 119
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 114
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 115
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 116
PSPCON (Parallel Slave Port Control) .................... 149
RCON (Reset Control) ....................................... 48, 123
RCSTAx (Receive Status and Control) .................... 241
SSPxADD (MSSP1 and MSSP2 Address) .............. 208
SSPxCON1 (MSSPx Control 1, I
2
C Mode) .............. 205
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 195
SSPxCON2 (MSSPx Control 2,
I
2
C Master Mode) ............................................. 206
SSPxSTAT (MSSPx Status, I
2
C Mode) ................... 204
SSPxSTAT (MSSPx Status, SPI Mode) .................. 194
STATUS .....................................................................77
STKPTR (Stack Pointer) ............................................ 64
T0CON (Timer0 Control) .......................................... 151
T1CON (Timer1 Control) .......................................... 155
T2CON (Timer2 Control) .......................................... 161
T3CON (Timer3 Control) .......................................... 163
T4CON (Timer4 Control) .......................................... 167
TXSTAx (Transmit Status and Control) ................... 240
WDTCON (Watchdog Timer Control) ....................... 287
RESET ............................................................................. 323
Reset ................................................................................. 47
Brown-out Reset (BOR) ............................................. 47
MCLR
Reset, During Power-Managed Modes .......... 47
MCLR
Reset, Normal Operation ................................ 47
Power-on Reset (POR) .............................................. 47
RESET Instruction ..................................................... 47
Stack Full Reset ......................................................... 47
Stack Underflow Reset .............................................. 47
Watchdog Timer (WDT) Reset .................................. 47
Resets .............................................................................. 281
Brown-out Reset (BOR) ........................................... 281
Oscillator Start-up Timer (OST) ............................... 281
Power-on Reset (POR) ............................................ 281
Power-up Timer (PWRT) ......................................... 281
RETFIE ............................................................................ 324
RETLW ............................................................................ 324
RETURN .......................................................................... 325
Return Address Stack ........................................................ 63
Return Stack Pointer (STKPTR) ........................................ 64
RLCF ............................................................................... 325
RLNCF ............................................................................. 326
RRCF ............................................................................... 326
RRNCF ............................................................................ 327
S
SCKx ................................................................................ 193
SDIx ................................................................................. 193
SDOx ............................................................................... 193
SEC_IDLE Mode ............................................................... 44
SEC_RUN Mode ................................................................ 40
Serial Clock, SCKx .......................................................... 193
Serial Data In (SDIx) ........................................................ 193
Serial Data Out (SDOx) ................................................... 193
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 327
Slave Select (SSx
) ........................................................... 193
SLEEP ............................................................................. 328
Sleep
OSC1 and OSC2 Pin States ...................................... 37
Software Simulator (MPLAB SIM) ................................... 344
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 281
SPI Mode (MSSP) ........................................................... 193
Associated Registers ............................................... 202
Bus Mode Compatibility ........................................... 201
Clock Speed, Interactions ........................................ 201
Effects of a Reset .................................................... 201
Enabling SPI I/O ...................................................... 197
Master Mode ............................................................ 198
Master/Slave Connection ......................................... 197
Operation ................................................................. 196
Operation in Power-Managed Modes ...................... 201
Serial Clock .............................................................. 193
Serial Data In ........................................................... 193
Serial Data Out ........................................................ 193
Slave Mode .............................................................. 199
Slave Select ............................................................. 193
Slave Select Synchronization .................................. 199
SPI Clock ................................................................. 198
SSPxBUF Register .................................................. 198
SSPxSR Register .................................................... 198
Typical Connection .................................................. 197
SSPOV ............................................................................ 229