Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 68  2003-2013 Microchip Technology Inc.
STATUS — — —NOV ZDCC ---x xxxx 37, 81
TMR0H Timer0 Register High Byte
0000 0000 37, 157
TMR0L Timer0 Register Low Byte
xxxx xxxx 37, 157
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
1111 1111 37, 155
OSCCON
— — — — LOCK PLLEN SCS1 SCS ---- 0000 27, 37
LVDCON
— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 37, 271
WDTCON
— — — — — — —SWDTE ---- ---0 37, 355
RCON IPEN
— —RITO PD POR BOR 0--1 11qq 37, 82,
123
TMR1H Timer1 Register High Byte
xxxx xxxx 37, 159
TMR1L Timer1 Register Low Byte
xxxx xxxx 37, 159
T1CON RD16
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 37, 159
TMR2 Timer2 Register
0000 0000 37, 162
PR2 Timer2 Period Register
1111 1111 37, 163
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 37, 162
SSPBUF SSP Receive Buffer/Transmit Register
xxxx xxxx 37, 189
SSPADD SSP Address Register in I
2
C Slave mode. SSP Baud Rate Reload Register in I
2
C Master mode. 0000 0000 37, 198
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 37, 199
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 37, 191
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
0000 0000 37, 201
ADRESH A/D Result Register High Byte
xxxx xxxx 38, 257
ADRESL A/D Result Register Low Byte
xxxx xxxx 38, 257
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 38, 249
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 38, 257
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 38, 251
CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 38, 173
CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 38, 172
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
0000 0000 38, 172
CCPR2H Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 38, 172
CCPR2L Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 38, 172
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 38, 172
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0
0000 0000 38, 172
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
0000 0000 38, 265
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
0000 0000 38, 259
TMR3H Timer3 Register High Byte
xxxx xxxx 38, 164
TMR3L Timer3 Register Low Byte
xxxx xxxx 38, 164
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 38, 164
PSPCON IBF OBF IBOV PSPMODE
— — — — 0000 ---- 38, 153
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator
modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X80 devices; always maintain these clear.
4: These bits have multiple functions depending on the CAN module mode selection.
5: Meaning of this register depends on whether this buffer is configured as transmit or receive.
6: RG5 is available as an input when MCLR
is disabled.
7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.
18F8680.book Page 68 Tuesday, January 29, 2013 1:32 PM