Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 436  2003-2013 Microchip Technology Inc.
FIGURE 27-14: PARALLEL SLAVE PORT TIMING (PIC18FXX8X)
TABLE 27-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18FXX8X)
Note: Refer to Figure 27-5 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param.
No.
Symbol Characteristic Min Max Units Conditions
62 T
DTV2WRH Data In Valid before WR  or CS 
(setup time)
20
25
—
—
ns
ns Extended Temp. range
63 T
WRH2DTIWR  or CS  to Data–In
Invalid (hold time)
PIC18FXX8X 20 — ns
PIC18LFXX8X 35 — ns
64 T
RDL2DTVRD  and CS  to Data–Out Valid —
—
80
90
ns
ns Extended Temp. range
65 T
RDH2DTIRD  or CS  to Data–Out Invalid 10 30 ns
66 T
IBFINH Inhibit of the IBF flag bit being cleared from
WR
 or CS 
—3 T
CY
18F8680.book Page 436 Tuesday, January 29, 2013 1:32 PM