Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 280  2003-2013 Microchip Technology Inc.
REGISTER 23-2: CANSTAT: CAN STATUS REGISTER (CONTINUED)
bit 4-0 Mode 1,2:
EICODE4:EICODE0: Interrupt Code bits in Mode 1 and Mode 2
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This
code indicates the source of the interrupt. Unlike ICODE bits in Mode 0, these bits may not be
copied directly to EWIN bits to map interrupted buffer to Access Bank area. If required, user
software may maintain a table in program memory to map EICODE bits to EWIN bits and access
interrupt buffer in Access Bank area.
Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity,
switch CAN module to Disable mode before putting the device to Sleep.
2: In Mode 2, if the buffer is configured as a receiver, EICODE bits will always contain
‘10000’ upon interrupt.
Legend: U = Unimplemented bit, read as ‘0’ - n = Value at POR
C = Clearable bit R = Readable bit W = Writable bit x = Bit is unknown
‘1’ = Bit is set ‘0’ = Bit is cleared
EICODE4:EICODE0 Value
No interrupt 00000
Error interrupt 00010
TXB2 interrupt 00100
TXB1 interrupt 00110
TXB0 interrupt 01000
RXB1 interrupt 10001/10000
(2)
RXB0 interrupt 10000
Wake-up interrupt 01110
RX/TX B0 interrupt 10010
(2)
RX/TX B1 interrupt 10011
(2)
RX/TX B2 interrupt 10100
(2)
RX/TX B3 interrupt 10101
(2)
RX/TX B4 interrupt 10110
(2)
RX/TX B4 interrupt 10111
(2)
18F8680.book Page 280 Tuesday, January 29, 2013 1:32 PM