Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 152  2003-2013 Microchip Technology Inc.
10.10 Parallel Slave Port (PSP)
PORTD also operates as an 8-bit wide Parallel Slave
Port, or microprocessor port, when control bit
PSPMODE (TRISE<4>) is set. It is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD/AD8 and WR control input
pin, RE1/WR
/AD9.
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD
/AD8 to be the
RD
input, RE1/WR/AD9 to be the WR input and
RE2/CS
/AD10 to be the CS (chip select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set). The A/D port configuration bits
PCFG2:PCFG0 (ADCON1<2:0>) must be set, which
will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS
and WR
lines are first detected low. A read from the PSP occurs
when both the CS
and RD lines are first detected low.
The PORTE I/O pins become control inputs for
the microprocessor port when bit PSPMODE
(PSPCON<4>) is set. In this mode, the user must make
sure that the TRISE<2:0> bits are set (pins are config-
ured as digital inputs) and the ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.
FIGURE 10-28: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Note: For PIC18F8X8X devices, the Parallel
Slave Port is available only in
Microcontroller mode.
Data Bus
WR LATD
RDx
QD
CK
EN
QD
EN
RD PORTD
pin
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
or
PORTD
RD LATD
Data Latch
TRIS Latch
18F8680.book Page 152 Tuesday, January 29, 2013 1:32 PM