Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 129
PIC18F6585/8585/6680/8680
FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS
FIGURE 10-7: BLOCK DIAGRAM OF RB3 PIN
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
INTx
I/O pin
(1)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU
bit (OPTION_REG<7>).
Data Latch
P
V
DD
QD
CK
Q
D
EN
Data Bus
WR LATB or
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
CCP2 or INT3
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
RD LATB
WR PORTB
RBPU
(2)
CK
D
Enable
(3)
CCP Output
RD PORTB
CCP Output
(3)
1
0
P
N
V
DD
VSS
I/O pin
(1)
Q
CCP2MX
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU
bit (INTCON2<7>).
3: For PIC18FXX85 parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration
register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
18F8680.book Page 129 Tuesday, January 29, 2013 1:32 PM