Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 97
PIC18F6525/6621/8525/8621
REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 RC2IE: USART2 Receive Interrupt Enable bit
1 = Enables the USART2 receive interrupt
0 = Disables the USART2 receive interrupt
bit 4 TX2IE: USART2 Transmit Interrupt Enable bit
1 = Enables the USART2 transmit interrupt
0 = Disables the USART2 transmit interrupt
bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the TMR4 to PR4 match interrupt
0 = Disables the TMR4 to PR4 match interrupt
bit 2-0 CCPxIE: CCPx Interrupt Enable bit (ECCP3, CCP4 and CCP5)
1 = Enables the CCPx interrupt
0 = Disables the CCPx interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown