Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 53
PIC18F6525/6621/8525/8621
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 34, 243
TMR3H Timer3 Register High Byte xxxx xxxx 34, 145
TMR3L Timer3 Register Low Byte xxxx xxxx 34, 145
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 34, 145
PSPCON
(5)
IBF OBF IBOV PSPMODE — — — — 0000 ---- 34, 129
SPBRG1 Enhanced USART1 Baud Rate Generator Register Low Byte 0000 0000 34, 217
RCREG1 Enhanced USART1 Receive Register 0000 0000 34, 224
TXREG1 Enhanced USART1 Transmit Register 0000 0000 34, 222
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 34, 214
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 34, 215
EEADRH
— — — — — — EE Addr Register High ---- --00 34, 83
EEADR Data EEPROM Address Register 0000 0000 34, 83
EEDATA Data EEPROM Data Register 0000 0000 34, 83
EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 34, 83
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 34, 80
IPR3
— — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 35, 100
PIR3
— — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 35, 94
PIE3
— — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 35, 97
IPR2
—CMIP— EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 35, 99
PIR2
—CMIF— EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 35, 93
PIE2
—CMIE— EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 35, 96
IPR1 PSPIP
(5)
ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 35, 98
PIR1 PSPIF
(5)
ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 35, 92
PIE1 PSPIE
(5)
ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 35, 95
MEMCON
(3)
EBDIS —WAIT1WAIT0— —WM1WM00-00 --00 35, 71
TRISJ
(3)
Data Direction Control Register for PORTJ 1111 1111 35, 127
TRISH
(3)
Data Direction Control Register for PORTH 1111 1111 35, 124
TRISG
— — — Data Direction Control Register for PORTG ---1 1111 35, 119
TRISF Data Direction Control Register for PORTF 1111 1111 35, 116
TRISE Data Direction Control Register for PORTE 1111 1111 35, 113
TRISD Data Direction Control Register for PORTD 1111 1111 35, 110
TRISC Data Direction Control Register for PORTC 1111 1111 35, 108
TRISB Data Direction Control Register for PORTB 1111 1111 35, 105
TRISA
— TRISA6
(1)
Data Direction Control Register for PORTA -111 1111 35, 121
LATJ
(3)
Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx 35, 127
LATH
(3)
Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx 35, 124
LATG
— — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 35, 121
LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 35, 119
LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx 35, 116
LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 35, 113
LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 35, 110
LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 35, 108
LATA
—LATA6
(1)
Read PORTA Data Latch, Write PORTA Data Latch
(1)
-xxx xxxx 35, 105
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other
oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6525/6621 devices and read as ‘0’.
4: RG5 is available only if MCLR
function is disabled in configuration.
5: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.