Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 52  2003-2013 Microchip Technology Inc.
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register)
N/A 56
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register) – value of FSR2 offset by value in WREG
N/A 56
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 33, 56
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 33, 56
STATUS
— — —NOVZDCC---x xxxx 33, 58
TMR0H Timer0 Register High Byte 0000 0000 33, 133
TMR0L Timer0 Register Low Byte xxxx xxxx 33, 133
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 33, 131
OSCCON
— — — — LOCK PLLEN SCS1 SCS0 ---- 0000 25, 33
LVDCON
— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 33, 255
WDTCON
— — — — — — —SWDTEN---- ---0 33, 267
RCON IPEN
— —RITO PD POR BOR 0--1 11qq 33, 59,
101
TMR1H Timer1 Register High Byte xxxx xxxx 33, 139
TMR1L Timer1 Register Low Byte xxxx xxxx 33, 139
T1CON RD16
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 33, 139
TMR2 Timer2 Register 0000 0000 33, 142
PR2 Timer2 Period Register 1111 1111 33, 142
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 33, 142
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 33, 181
SSPADD MSSP Address Register in I
2
C Slave mode. MSSP Baud Rate Reload Register in I
2
C Master mode. 0000 0000 33, 181
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 33, 174
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 33, 175
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 33, 185
ADRESH A/D Result Register High Byte xxxx xxxx 33, 241
ADRESL A/D Result Register Low Byte xxxx xxxx 33, 241
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 34, 233
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 34, 234
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 34, 235
CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 34, 172
CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 34, 172
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 34, 157
CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte xxxx xxxx 34, 172
CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 34, 172
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 34, 157
CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte xxxx xxxx 34, 172
CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 34, 172
CCP3CON P3M1 P3M0 DC3B1 DC2B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 34, 157
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 34, 169
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 34, 249
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other
oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6525/6621 devices and read as ‘0’.
4: RG5 is available only if MCLR
function is disabled in configuration.
5: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.