Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 51
PIC18F6525/6621/8525/8621
TABLE 4-3: REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 32, 42
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 32, 42
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 32, 42
STKPTR STKFUL STKUNF
— Return Stack Pointer 00-0 0000 32, 43
PCLATU
— — — Holding Register for PC<20:16> ---0 0000 32, 44
PCLATH Holding Register for PC<15:8> 0000 0000 32, 44
PCL PC Low Byte (PC<7:0>) 0000 0000 32, 44
TBLPTRU
— —bit 21
(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 32, 69
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 32, 69
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 32, 69
TABLAT Program Memory Table Latch 0000 0000 32, 69
PRODH Product Register High Byte xxxx xxxx 32, 85
PRODL Product Register Low Byte xxxx xxxx 32, 85
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 32, 89
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 32, 90
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 32, 91
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 56
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented
(not a physical register)
N/A 56
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented
(not a physical register)
N/A 56
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 56
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented
(not a physical register) – value of FSR0 offset by value in WREG
N/A 56
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 32, 56
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 32, 56
WREG Working Register xxxx xxxx 32
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 56
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented
(not a physical register)
N/A 56
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented
(not a physical register)
N/A 56
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 56
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register) – value of FSR1 offset by value in WREG
N/A 56
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 32, 56
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 33, 56
BSR
— — — — Bank Select Register ---- 0000 33, 55
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 56
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented
(not a physical register)
N/A 56
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented
(not a physical register)
N/A 56
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as a port pin in RCIO and ECIO Oscillator modes only and read ‘0’ in all other
oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6525/6621 devices and read as ‘0’.
4: RG5 is available only if MCLR
function is disabled in configuration.
5: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.