Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 354  2003-2013 Microchip Technology Inc.
FIGURE 27-20: MASTER SSP I
2
C™ BUS START/STOP BITS TIMING WAVEFORMS
TABLE 27-21: MASTER SSP I
2
C™ BUS START/STOP BITS REQUIREMENTS
FIGURE 27-21: MASTER SSP I
2
C™ BUS DATA TIMING
Note: Refer to Figure 27-4 for load conditions.
91
93
SCL
SDA
Start
Condition
Stop
Condition
90
92
Param.
No.
Symbol Characteristic Min Max Units Conditions
90 T
SU:STA Start Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Repeated Start
condition
400 kHz mode 2(T
OSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
91 T
HD:STA Start Condition
Hold Time
100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the
first clock pulse is
generated
400 kHz mode 2(T
OSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
92 T
SU:STO Stop Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1) — ns
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
93 T
HD:STO Stop Condition
Hold Time
100 kHz mode 2(TOSC)(BRG + 1) — ns
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode
(1)
2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I
2
C pins.
Note: Refer to Figure 27-4 for load conditions.
90
91 92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out