Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 350  2003-2013 Microchip Technology Inc.
FIGURE 27-17: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
TABLE 27-18: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL
SS
 to SCK  or SCK  Input TCY —ns
71 TscH SCK Input High Time
(Slave mode)
Continuous 1.25 T
CY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode)
Continuous 1.25 T
CY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time PIC18F6525/6621/
8525/8621
—25ns
PIC18LF6X2X/8X2X 45 ns
76 TdoF SDO Data Output Fall Time — 25 ns
77 TssH2doZ SS
 to SDO Output High-impedance 10 50 ns
78 TscR SCK Output Rise Time
(Master mode)
PIC18F6525/6621/
8525/8621
—25ns
PIC18LF6X2X/8X2X — 45 ns
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV
SDO Data Output Valid after SCK
Edge
PIC18F6525/6621/
8525/8621
—50ns
PIC18LF6X2X/8X2X — 100 ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb bit 6 - - - - - -1 LSb
77
MSb In bit 6 - - - -1
LSb In
80
83
Note: Refer to Figure 27-4 for load conditions.