Datasheet
2003-2013 Microchip Technology Inc. DS39612C-page 35
PIC18F6525/6621/8525/8621
IPR3 Feature1 Feature2 --11 1111 --11 1111 --uu uuuu
PIR3 Feature1 Feature2 --00 0000 --00 0000 --uu uuuu
PIE3 Feature1 Feature2 --00 0000 --00 0000 --uu uuuu
IPR2 Feature1 Feature2 -1-1 1111 -1-1 1111 -u-u uuuu
PIR2 Feature1 Feature2 -0-0 0000 -0-0 0000 -u-u uuuu
(1)
PIE2 Feature1 Feature2 -0-0 0000 -0-0 0000 -u-u uuuu
IPR1 Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
PIR1 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
(1)
PIE1 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
MEMCON
(9)
Feature1 Feature2 0-00 --00 0-00 --00 u-uu --uu
TRISJ Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
TRISH
Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
TRISG Feature1 Feature2 ---1 1111 ---1 1111 ---u uuuu
TRISF Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
TRISE Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
TRISD Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
TRISC Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
TRISB Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
TRISA
(5,6)
Feature1 Feature2 -111 1111
(5)
-111 1111
(5)
-uuu uuuu
(5)
LATJ Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
LATH
Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
LATG Feature1 Feature2 ---x xxxx ---u uuuu ---u uuuu
LATF Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
LATE Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
LATD Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
LATC Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
LATB Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
LATA
(5,6)
Feature1 Feature2 -xxx xxxx
(5)
-uuu uuuu
(5)
-uuu uuuu
(5)
PORTJ Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
PORTH
Feature1 Feature2 0000 xxxx 0000 uuuu uuuu uuuu
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR
function is disabled, PORTG<5> is a read-only bit.
8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode.