Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 347
PIC18F6525/6621/8525/8621
FIGURE 27-15: EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)
73 TdiV2scH,
TdiV2scL
Setup Time of SDI Data Input to SCK Edge 100 — ns
73A T
B2B Last Clock Edge of Byte 1 to the 1st Clock Edge of
Byte 2
1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TdoR SDO Data Output Rise Time PIC18F6525/6621/
8525/8621
—25ns
PIC18LF6X2X/8X2X — 45 ns
76 TdoF SDO Data Output Fall Time — 25 ns
78 TscR SCK Output Rise Time
(Master mode)
PIC18F6525/6621/
8525/8621
—25ns
PIC18LF6X2X/8X2X — 45 ns
79 TscF SCK Output Fall Time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV
SDO Data Output Valid after
SCK Edge
PIC18F6525/6621/
8525/8621
—50ns
PIC18LF6X2X/8X2X — 100 ns
Param.
No.
Symbol Characteristic Min Max Units Conditions
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 27-4 for load conditions.