Datasheet
2003-2013 Microchip Technology Inc. DS39612C-page 33
PIC18F6525/6621/8525/8621
FSR1L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
BSR Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuu
INDF2 Feature1 Feature2 N/A N/A N/A
POSTINC2 Feature1 Feature2 N/A N/A N/A
POSTDEC2 Feature1 Feature2 N/A N/A N/A
PREINC2 Feature1 Feature2 N/A N/A N/A
PLUSW2 Feature1 Feature2 N/A N/A N/A
FSR2H Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuu
FSR2L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS Feature1 Feature2 ---x xxxx ---u uuuu ---u uuuu
TMR0H Feature1 Feature2 0000 0000 uuuu uuuu uuuu uuuu
TMR0L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
OSCCON Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuu
LVDCON Feature1 Feature2 --00 0101 --00 0101 --uu uuuu
WDTCON Feature1 Feature2 ---- ---0 ---- ---0 ---- ---u
RCON
(4)
Feature1 Feature2 0--1 11qq 0--1 qquu u--1 qquu
TMR1H Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON Feature1 Feature2 0-00 0000 u-uu uuuu u-uu uuuu
TMR2 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
PR2 Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
T2CON Feature1 Feature2 -000 0000 -000 0000 -uuu uuuu
SSPBUF Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
SSPSTAT Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
SSPCON1 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
SSPCON2 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
ADRESH Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR
function is disabled, PORTG<5> is a read-only bit.
8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode.