Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 32  2003-2013 Microchip Technology Inc.
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU Feature1 Feature2 ---0 0000 ---0 0000 ---0 uuuu
(3)
TOSH Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
(3)
TOSL Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
(3)
STKPTR Feature1 Feature2 00-0 0000 uu-0 0000 uu-u uuuu
(3)
PCLATU Feature1 Feature2 ---0 0000 ---0 0000 ---u uuuu
PCLATH Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
PCL Feature1 Feature2 0000 0000 0000 0000 PC + 2
(2)
TBLPTRU Feature1 Feature2 --00 0000 --00 0000 --uu uuuu
TBLPTRH Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
TBLPTRL Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
TABLAT Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
PRODH Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON Feature1 Feature2 0000 000x 0000 000u uuuu uuuu
(1)
INTCON2 Feature1 Feature2 1111 1111 1111 1111 uuuu uuuu
(1)
INTCON3 Feature1 Feature2 1100 0000 1100 0000 uuuu uuuu
(1)
INDF0 Feature1 Feature2 N/A N/A N/A
POSTINC0 Feature1 Feature2 N/A N/A N/A
POSTDEC0 Feature1 Feature2 N/A N/A N/A
PREINC0 Feature1 Feature2 N/A N/A N/A
PLUSW0 Feature1 Feature2 N/A N/A N/A
FSR0H Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuu
FSR0L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
WREG Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 Feature1 Feature2 N/A N/A N/A
POSTINC1 Feature1 Feature2 N/A N/A N/A
POSTDEC1 Feature1 Feature2 N/A N/A N/A
PREINC1 Feature1 Feature2 N/A N/A N/A
PLUSW1 Feature1 Feature2 N/A N/A N/A
FSR1H Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR
function is disabled, PORTG<5> is a read-only bit.
8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode.