Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 27
PIC18F6525/6621/8525/8621
If the main oscillator is configured for HS mode with
PLL active, an oscillator start-up time (T
OST) plus an
additional PLL time-out (T
PLL) will occur. The PLL time-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for HS+PLL mode, is shown in Figure 2-10.
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(HS WITH PLL ACTIVE, SCS1 = 1)
If the main oscillator is configured for EC mode with PLL
active, only PLL time-out (T
PLL) will occur. The PLL time-
out is typically 2 ms and allows the PLL to lock to the
main oscillator frequency. A timing diagram, indicating
the transition from the Timer1 oscillator to the main
oscillator for EC with PLL active, is shown in Figure 2-11.
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1
(EC WITH PLL ACTIVE, SCS1 = 1)
Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter
PC PC + 2
Note: T
OST = 1024 TOSC (drawing not to scale).
T1OSI
Clock
TOST
Q3
PC + 4
TPLL
TOSC
TT1P
TSCS
Q4
PLL Clock
Input
1 23 4 5678
Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter
PC PC + 2
T1OSI
Clock
Q3
PC + 4
TPLL
TOSC
TT1P
TSCS
Q4
PLL Clock
Input
12345678