Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 111
PIC18F6525/6621/8525/8621
10.4 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individually configurable as an input
or output.
PORTD is multiplexed with the system bus as the
external memory interface. I/O port functions are only
available when the system bus is disabled by setting
the EBDIS bit in the MEMCOM register
(MEMCON<7>). When operating as the external
memory interface, PORTD is the low-order byte of the
multiplexed address/data bus (AD7:AD0).
PORTD can also be configured as an 8-bit wide
microprocessor port (Parallel Slave Port) by setting
control bit PSPMODE (TRISE<4>). In this mode, the
input buffers are TTL. See Section 10.10 “Parallel
Slave Port” for additional information on the Parallel
Slave Port (PSP).
EXAMPLE 10-4: INITIALIZING PORTD
FIGURE 10-9: PORTD BLOCK DIAGRAM
IN I/O PORT MODE
Note: On a Power-on Reset, these pins are
configured as digital inputs.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Data
Bus
WR LATD
WR TRISD
RD PORTD
Data Latch
TRIS Latch
RD TRISD
Schmitt
Trigger
Input
Buffer
I/O pin
(1)
QD
CK
QD
CK
EN
QD
EN
RD LATD
or
PORTD
Note 1: I/O pins have diode protection to V
DD and VSS.