Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 565
PIC18F87K90 FAMILY
Timing Diagrams
A/D Conversion......................................................... 543
Automatic Baud Rate Calculation ............................. 358
Auto-Wake-up Bit (WUE) During Normal
Operation .......................................................... 365
Auto-Wake-up Bit (WUE) During Sleep .................... 365
Baud Rate Generator with Clock Arbitration ............. 336
BRG Overflow Sequence.......................................... 358
BRG Reset Due to SDAx Arbitration During
Start Condition .................................................. 345
Brown-out Reset (BOR)............................................ 528
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 346
Bus Collision During a Repeated Start
Condition (Case 2)............................................ 346
Bus Collision During a Start Condition
(SCLx = 0)......................................................... 345
Bus Collision During a Stop Condition
(Case 1) ............................................................ 347
Bus Collision During a Stop Condition
(Case 2) ............................................................ 347
Bus Collision During Start Condition
(SDAx Only)...................................................... 344
Bus Collision for Transmit and Acknowledge............ 343
Capture/Compare/PWM (ECCP1, ECCP2) .............. 532
CLKO and I/O ........................................................... 527
Clock Synchronization .............................................. 329
Clock/Instruction Cycle ............................................... 90
EUSART Asynchronous Reception .......................... 363
EUSART Asynchronous Transmission ..................... 360
EUSART Asynchronous Transmission
(Back-to-Back) .................................................. 360
EUSART Synchronous Master Transmission ........... 367
EUSART Synchronous Transmission
(Master/Slave) .................................................. 541
EUSART/AUSART Synchronous Receive
(Master/Slave) .................................................. 541
Example SPI Master Mode (CKE = 0) ...................... 533
Example SPI Master Mode (CKE = 1) ...................... 534
Example SPI Slave Mode (CKE = 0) ........................ 535
Example SPI Slave Mode (CKE = 1) ........................ 536
External Clock........................................................... 525
Fail-Safe Clock Monitor (FSCM)............................... 446
First Start Bit Timing ................................................. 337
Full-Bridge PWM Output ........................................... 262
Half-Bridge PWM Output .................................. 260, 267
High/Low-Voltage Detect Characteristics ................. 530
High-Voltage Detect Operation (VDIRMAG = 1)....... 404
I
2
C Acknowledge Sequence ..................................... 342
I
2
C Bus Data............................................................. 538
I
2
C Bus Start/Stop Bits.............................................. 537
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 340
I
2
C Master Mode (7-Bit Reception)........................... 341
I
2
C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001).............................................. 325
I
2
C Slave Mode (10-Bit Reception, SEN = 0) ........... 326
I
2
C Slave Mode (10-Bit Reception, SEN = 1) ........... 331
I
2
C Slave Mode (10-Bit Transmission)...................... 327
I
2
C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011).............................................. 323
I
2
C Slave Mode (7-Bit Reception, SEN = 0) ............. 322
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............. 330
I
2
C Slave Mode (7-Bit Transmission)........................ 324
I
2
C Slave Mode General Call Address Sequence
(7 or 10-Bit Addressing Mode).......................... 332
I
2
C Stop Condition Receive or Transmit Mode......... 342
LCD Interrupt Timing in Quarter Duty Cycle Drive ... 298
LCD Reference Ladder Power Mode Switching ....... 283
LCD Sleep Entry/Exit When SLPEN = 1 or CS = 00 299
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 403
MSSP I
2
C Bus Data ................................................. 539
MSSP I
2
C Bus Start/Stop Bits.................................. 539
PWM Auto-Shutdown with Auto-Restart Enabled,
PxRSEN = 1 ..................................................... 266
PWM Auto-Shutdown with Firmware Restart,
PxRSEN = 0 ..................................................... 266
PWM Direction Change ............................................ 263
PWM Direction Change at Near 100%
Duty Cycle ........................................................ 264
PWM Output ............................................................. 248
PWM Output (Active-High) ....................................... 258
PWM Output (Active-Low) ........................................ 259
Repeated Start Condition ......................................... 338
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ...... 528
Send Break Character Sequence............................. 366
Slave Synchronization .............................................. 309
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT)............................................. 73
SPI Mode (Master Mode) ......................................... 308
SPI Mode (Slave Mode, CKE = 0)............................ 310
SPI Mode (Slave Mode, CKE = 1)............................ 310
Steering Event at Beginning of Instruction
(STRSYNC = 1)................................................ 270
Steering Event at End of Instruction
(STRSYNC = 0)................................................ 270
Synchronous Master Transmission
(Through TXEN) ............................................... 368
Synchronous Reception (Master Mode, SREN) ....... 369
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD), Case 1 .......................................... 73
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD), Case 2 .......................................... 73
Time-out Sequence on Power-up
(MCLR
Tied to VDD, VDD Rise TPWRT) ............... 72
Timer Pulse Generation............................................ 234
Timer0 and Timer1 External Clock ........................... 531
Timer1 Gate Count Enable Mode............................. 193
Timer1 Gate Single Pulse Mode............................... 196
Timer1 Gate Single Pulse/Toggle
Combined Mode ............................................... 197
Timer1 Gate Toggle Mode........................................ 195
Timer3/5/7 Gate Count Enable Mode....................... 206
Timer3/5/7 Gate Single Pulse Mode......................... 208
Timer3/5/7 Gate Single Pulse/Toggle
Combined Mode ............................................... 209
Timer3/5/7 Gate Toggle Mode.................................. 207
Transition for Entry to Idle Mode ................................ 59
Transition for Entry to SEC_RUN Mode ..................... 55
Transition for Entry to Sleep Mode ............................. 58
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 444
Transition for Wake from Idle to Run Mode................ 59
Transition for Wake from Sleep (HSPLL) ................... 58
Transition from RC_RUN Mode to
PRI_RUN Mode.................................................. 57
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ................................... 55
Transition to RC_RUN Mode...................................... 57
Type-A in 1/2 MUX, 1/2 Bias Drive........................... 288