Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 529
PIC18F87K90 FAMILY
TABLE 31-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — sVDD = 3.3-5.0V,
-40°C to +85°C
5——
sVDD = 3.3-5.0V
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
—4.00— ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period — 65.5 140 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—s
35 T
BOR Brown-out Reset Pulse Width 200 — — sVDD  BVDD
(see D005)
36 T
IRVST Time for Internal Reference
Voltage to become Stable
—25— s
37 T
HLVD High/Low-Voltage Detect Pulse Width 200 — — sVDD  VHLVD
38 TCSD CPU Start-up Time 5 — 10 s
39 T
IOBST Time for INTOSC to Stabilize — 1 — s