Datasheet

PIC18F87K90 FAMILY
DS39957D-page 372  2009-2011 Microchip Technology Inc.
22.4.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode, and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RCxIE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 75
PIR1
— ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF 77
PIE1 — ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE 77
IPR1 — ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP 77
PIR3
TMR5GIF LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 77
PIE3 TMR5GIE LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 77
IPR3 TMR5GIP LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 77
RCSTA1 SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 77
RCREG1 EUSART1 Receive Register 77
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 77
BAUDCON1
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 79
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 76
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 77
RCSTA2 SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 81
RCREG2 EUSART2 Receive Register 82
TXSTA2 CSRC
TX9 TXEN SYNC SENDB BRGH TRMT TX9D 81
BAUDCON2
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 81
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 82
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 82
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.