Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 255
PIC18F87K90 FAMILY
19.2 Capture Mode
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
ECCPx pin. An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every fourth rising edge
•Every 16
th
rising edge
The event is selected by the mode select bits,
CCPxM<3:0> (CCPxCON register<3:0>). When a
capture is made, the interrupt request flag bit, CCPxIF,
is set (see Table 19-2). The flag must be cleared by
software. If another capture occurs before the value in
the CCPRxH/L register is read, the old captured value
is overwritten by the new captured value.
19.2.1 ECCP PIN CONFIGURATION
In Capture mode, the appropriate ECCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
19.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each ECCP module is
selected in the CCPTMRS0 register (Register 19-2).
19.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false interrupts.
The interrupt flag bit, CCPxIF, should also be cleared
following any such change in operating mode.
19.2.4 ECCP PRESCALER
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCPxM<3:0>). Whenever the
ECCP module is turned off, or Capture mode is
disabled, the prescaler counter is cleared. This means
that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 19-1 provides the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 19-1: CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
TABLE 19-2: ECCP1/2/3 INTERRUPT FLAG
BITS
ECCP Module Flag Bit
1 PIR3<1>
2 PIR3<2>
3 PIR4<0>
Note: If the ECCPx pin is configured as an
output, a write to the PORT can cause a
capture condition.
CLRF CCP1CON ; Turn ECCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and ECCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF
TMR3
Enable
Q1:Q4
CCP1CON<3:0>
ECCP1 Pin
TMR1
Enable
C1TSEL0
TMR3H TMR3L
4
4
C1TSEL1
C1TSEL2
C1TSEL0
C1TSEL1
C1TSEL2
Prescaler
 1, 4, 16
and
Edge Detect