Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 171
PIC18F87K90 FAMILY
TABLE 11-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
RE7/ECCP2/
P2A/SEG31
RE7 0 O DIG LATE<7> data output.
1 I ST PORTE<7> data input.
ECCP2
(1)
0 O DIG ECCP2 compare/PWM output; takes priority over port data.
1 I ST ECCP2 capture input.
P2A 0 O — ECCP2 PWM Output A. May be configured for tri-state during
Enhanced PWM shutdown event.
SEG31 1 O ANA Segment 31 analog output for LCD; disables digital output.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 78
LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 78
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 78
LCDCON
LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 83
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 83
ODCON1
SSP1OD CCP2OD CCP1OD — — — — SSP2OD 81
ODCON2 CCP10OD
(2)
CCP9OD
(2)
CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD 81
PADCFG1 RDPU REPU RJPU
(1)
— — RTSECSEL1 RTSECSEL0 — 80
Legend: Shaded cells are not used by PORTE.
Note 1: This bit is not available in 64-pin devices.
2: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).
TABLE 11-10: PORTE FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
2: This bit is unimplemented in PIC18FX5K90 devices.