Datasheet

© 2009 Microchip Technology Inc. DS39663F-page 403
PIC18F87J10 FAMILY
SSPOV Status Flag ......................................................... 229
SSPxSTAT Register
R/W
Bit ............................................................. 209, 211
SSx
.................................................................................. 193
Stack Full/Underflow Resets .............................................. 65
SUBFSR .......................................................................... 339
SUBFWB .......................................................................... 328
SUBLW ............................................................................ 329
SUBULNK ........................................................................ 339
SUBWF ............................................................................ 329
SUBWFB .......................................................................... 330
SWAPF ............................................................................ 330
T
Table Pointer Operations (table) ........................................ 88
Table Reads/Table Writes ................................................. 65
TBLRD ............................................................................. 331
TBLWT ............................................................................. 332
Timer0 .............................................................................. 151
Associated Registers ............................................... 153
Operation ................................................................. 152
Overflow Interrupt .................................................... 153
Prescaler .................................................................. 153
Switching Assignment ...................................... 153
Prescaler Assignment (PSA Bit) .............................. 153
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 153
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 152
Source Edge Select (T0SE Bit) ................................ 152
Source Select (T0CS Bit) ......................................... 152
Timer1 .............................................................................. 155
16-Bit Read/Write Mode ........................................... 157
Associated Registers ............................................... 159
Interrupt .................................................................... 158
Low-Power Option ................................................... 157
Operation ................................................................. 156
Oscillator .......................................................... 155, 157
Layout Considerations ..................................... 158
Oscillator, as Secondary Clock .................................. 34
Overflow Interrupt .................................................... 155
Resetting, Using the ECCP
Special Event Trigger ...................................... 158
Special Event Trigger (ECCP) ................................. 180
TMR1H Register ...................................................... 155
TMR1L Register ....................................................... 155
Use as a Clock Source ............................................ 157
Use as a Real-Time Clock ....................................... 158
Timer2 .............................................................................. 161
Associated Registers ............................................... 162
Interrupt .................................................................... 162
Operation ................................................................. 161
Output ...................................................................... 162
PR2 Register ............................................................ 181
TMR2 to PR2 Match Interrupt .................................. 181
Timer3 .............................................................................. 163
16-Bit Read/Write Mode ........................................... 165
Associated Registers ............................................... 165
Operation ................................................................. 164
Oscillator .......................................................... 163, 165
Overflow Interrupt ............................................ 163, 165
Special Event Trigger (ECCP) ................................. 165
TMR3H Register ...................................................... 163
TMR3L Register ....................................................... 163
Timer4 ............................................................................. 167
Associated Registers ............................................... 168
MSSP Clock Shift .................................................... 168
Operation ................................................................. 167
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 167
Prescaler. See Prescaler, Timer4.
TMR4 Register ........................................................ 167
TMR4 to PR4 Match Interrupt .......................... 167, 168
Timing Diagrams
A/D Conversion ....................................................... 382
Asynchronous Reception ......................................... 252
Asynchronous Transmission ................................... 250
Asynchronous Transmission (Back to Back) ........... 250
Automatic Baud Rate Calculation ............................ 248
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 253
Auto-Wake-up Bit (WUE) During Sleep ................... 253
Baud Rate Generator with Clock Arbitration ............ 226
BRG Overflow Sequence ........................................ 248
BRG Reset Due to SDAx Arbitration During
Start Condition ................................................. 235
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 236
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 236
Bus Collision During a Start Condition
(SCLx = 0) ....................................................... 235
Bus Collision During a Stop
Condition (Case 1) ........................................... 237
Bus Collision During a Stop
Condition (Case 2) ........................................... 237
Bus Collision During Start Condition
(SDAx Only) ..................................................... 234
Bus Collision for Transmit and Acknowledge .......... 233
Capture/Compare/PWM (Including
ECCP Modules) ............................................... 372
CLKO and I/O .......................................................... 366
Clock Synchronization ............................................. 219
Clock/Instruction Cycle .............................................. 66
EUSART Synchronous Receive
(Master/Slave) ................................................. 381
EUSART Synchronous Transmission
(Master/Slave) ................................................. 381
Example SPI Master Mode (CKE = 0) ..................... 373
Example SPI Master Mode (CKE = 1) ..................... 374
Example SPI Slave Mode (CKE = 0) ....................... 375
Example SPI Slave Mode (CKE = 1) ....................... 376
External Clock (All Modes Except PLL) ................... 364
External Memory Bus for Sleep
(Extended Microcontroller Mode) ............ 102, 104
External Memory Bus for TBLRD
(Extended Microcontroller Mode) ............ 102, 104
Fail-Safe Clock Monitor ........................................... 291
First Start Bit Timing ................................................ 227
Full-Bridge PWM Output .......................................... 185
Half-Bridge PWM Output ......................................... 184
I
2
C Acknowledge Sequence .................................... 232
I
2
C Bus Data ............................................................ 377
I
2
C Bus Start/Stop Bits ............................................ 377
I
2
C Master Mode (7 or 10-Bit Transmission) ........... 230
I
2
C Master Mode (7-Bit Reception) ......................... 231