Datasheet

PIC18F87J10 FAMILY
DS39663F-page 370 © 2009 Microchip Technology Inc.
FIGURE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
TABLE 27-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30
T
MCLMCLR Pulse Width (low) 2 — — μs
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
3.5 4.1 4.9 ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 57.4 66 77.7 ms
34
T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—μs
38 T
CSD CPU Start-up Time — 200 — μs
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 27-3 for load conditions.