Datasheet
PIC18F87J10 FAMILY
DS39663F-page 206 © 2009 Microchip Technology Inc.
REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I
2
C™ MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT/
ADMSK5
(1)
ACKEN/
ADMSK4
RCEN/
ADMSK3
PEN/
ADMSK2
RSEN/
ADMSK1
SEN
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT/ADMSK5: Acknowledge Data bit (Master Receive mode only)
(1)
In Master Receive mode:
1 = Not Acknowledge
0 = Acknowledge
In Slave mode:
1 = Address masking of ADD5 enabled
0 = Address masking of ADD5 disabled
bit 4 ACKEN/ADMSK4: Acknowledge Sequence Enable bit
In Master Receive mode:
(2)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
In Slave mode:
1 = Address masking of ADD4 enabled
0 = Address masking of ADD4 disabled
bit 3 RCEN/ADMSK3: Receive Enable bit (Master Receive mode only)
In Master Receive mode:
(2)
1 = Enables Receive mode for I
2
C
0 = Receive Idle
In Slave mode:
1 = Address masking of ADD3 enabled
0 = Address masking of ADD3 disabled
bit 2 PEN/ADMSK2: Stop Condition Enable bit
In Master mode:
(2)
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
In Slave mode:
1 = Address masking of ADD2 enabled
0 = Address masking of ADD2 disabled
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: For bits, ACKEN, RCEN, PEN, RSEN, SEN: If the I
2
C module is active, these bits may not be set (no
spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).