Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 478  2003-2013 Microchip Technology Inc.
SLEEP ...................................................................... 400
SUBFWP................................................................... 400
SUBLW .....................................................................401
SUBWF ..................................................................... 401
SUBWFB................................................................... 402
SWAPF ..................................................................... 402
TBLRD ...................................................................... 403
TBLWT......................................................................404
TSTFSZ .................................................................... 405
XORLW.....................................................................405
XORWF..................................................................... 406
Summary Table......................................................... 368
INT Interrupt (RB0/INT).
See Interrupt Sources.
INTCON Registers ............................................................ 111
Inter-Integrated Circuit. See I
2
C.
Interrupt Sources...............................................................345
A/D Conversion Complete ........................................253
Capture Complete (CCP)..........................................170
Compare Complete (CCP)........................................171
ECAN Module ...........................................................342
INT0 ..........................................................................124
Interrupt-on-Change
(RB7:RB4)......................................................... 128
PORTB, Interrupt-on-Change ...................................124
RB0/INT Pin, External...............................................124
TMR0 ........................................................................ 124
TMR0 Overflow ......................................................... 157
TMR1 Overflow ................................................. 159, 161
TMR2 to PR2 Match ................................................. 163
TMR2 to PR2 Match (PWM) .....................162, 173, 177
TMR3 Overflow ................................................. 164, 166
Interrupts........................................................................... 109
Context Saving During
Interrupts........................................................... 124
Control Registers ......................................................111
Enable Registers....................................................... 117
Flag Registers...........................................................114
Logic (diagram) ......................................................... 110
Priority Registers....................................................... 120
Reset Control Registers............................................123
Interrupts, Flag Bits
CCP Flag (CCPxIF Bit) .............................169, 170, 171
IORLW .............................................................................. 388
IORWF .............................................................................. 388
IPR Registers ....................................................................120
L
LFSR ................................................................................. 389
Listen Only Mode .............................................................. 328
Look-up Tables
Computed GOTO........................................................58
Table Reads/Table Writes ..........................................58
Loopback Mode................................................................. 328
Low-Voltage Detect...........................................................269
Characteristics ..........................................................424
Converter Characteristics ......................................... 424
Effects of a Reset...................................................... 273
Operation .................................................................. 272
Current Consumption........................................ 273
During Sleep .....................................................273
Reference Voltage Set Point............................. 273
Typical Application ....................................................269
Low-Voltage ICSP Programming ......................................363
LVD. See Low-Voltage Detect.
M
Master SSP I
2
C Bus
Data Requirements................................................... 444
Master SSP I
2
C Bus Start/Stop Bits
Requirements ........................................................... 443
Master Synchronous Serial Port (MSSP).
See MSSP.
Memory Organization
Data Memory .............................................................. 59
PIC18F8X8X Program Memory Modes ...................... 51
Extended Microcontroller.................................... 51
Microcontroller .................................................... 51
Microprocessor................................................... 51
Microprocessor with
Boot Block .................................................. 51
Program Memory........................................................ 51
Memory Programming Requirements............................... 425
Migration from High-End to
Enhanced Devices.................................................... 471
Migration from Mid-Range to
Enhanced Devices.................................................... 470
MOVF ............................................................................... 389
MOVFF ............................................................................. 390
MOVLB ............................................................................. 390
MOVLW ............................................................................ 391
MOVWF ............................................................................ 391
MPLAB ASM30 Assembler,
Linker, Librarian........................................................ 408
MPLAB ICD 2 In-Circuit Debugger ................................... 409
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator.................................................... 409
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator.................................................... 409
MPLAB Integrated Development
Environment Software .............................................. 407
MPLAB PM3 Device Programmer .................................... 409
MPLINK Object Linker/
MPLIB Object Librarian............................................. 408
MSSP................................................................................ 189
ACK
Pulse ........................................................ 202, 203
Clock Stretching........................................................ 208
10-bit Slave Receive Mode
(SEN = 1).................................................. 208
10-bit Slave Transmit Mode.............................. 208
7-bit Slave Receive Mode
(SEN = 1).................................................. 208
7-bit Slave Transmit Mode................................ 208
Clock Synchronization and the
CKP Bit............................................................. 209
Control Registers (general)....................................... 189
I
2
C Mode .................................................................. 198
Acknowledge Sequence Timing ....................... 222
Baud Rate Generator ....................................... 215
Bus Collision
During a Repeated
Start Condition.................................. 226
Bus Collision During a
Start Condition.......................................... 224
Bus Collision During a
Stop Condition.......................................... 227
Clock Arbitration ............................................... 216
Effect of a Reset............................................... 223
I
2
C Clock Rate w/BRG ..................................... 215
18F8680.book Page 478 Tuesday, January 29, 2013 1:32 PM