Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 431
PIC18F6585/8585/6680/8680
TABLE 27-9: PROGRAM MEMORY READ TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V)
FIGURE 27-9: PROGRAM MEMORY WRITE TIMING DIAGRAM
Param.
No
Symbol Characteristics Min Typ Max Units
150 T
ADV2ALL Address Out Valid to ALE (address
setup time)
0.25 TCY – 10 — — ns
151 T
ALL2ADL ALE  to Address Out Invalid (address
hold time)
5——ns
155 T
ALL2OELALE to OE  10 0.125 TCY —ns
160 T
ADZ2OEL AD High-Z to OE (bus release to OE)0——ns
161 T
OEH2ADDOE  to AD Driven 0.125 TCY – 5 — — ns
162 T
ADV2OEH LS Data Valid before OE (data setup time) 20 — — ns
163 T
OEH2ADL OE  to Data In Invalid (data hold time) 0 — — ns
164 T
ALH2ALL ALE Pulse Width — 0.25 TCY —ns
165 T
OEL2OEHOE Pulse Width 0.5 TCY – 5 0.5 TCY —ns
166 T
ALH2ALHALE  to ALE  (cycle time) — 1 TCY —ns
167 T
ACC Address Valid to Data Valid 0.75 TCY – 25 — — ns
168 T
OE OE  to Data Valid — 0.5 TCY – 25 ns
169 T
ALL2OEHALE to OE  0.625 TCY – 10 — 0.625 TCY + 10 ns
171 T
ALH2CSL Chip Select Active to ALE  ——10ns
171A T
UBL2OEH AD Valid to Chip Select Active 0.25 TCY – 20 — — ns
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
ALE
Address
Data
156
150
151
153
AD<15:0>
Address
WRH or
WRL
UB or
LB
157
154
157A
Address
A<19:16>
Address
BA0
166
CE
171
171A
18F8680.book Page 431 Tuesday, January 29, 2013 1:32 PM