Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 430  2003-2013 Microchip Technology Inc.
TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS
FIGURE 27-8: PROGRAM MEMORY READ TIMING DIAGRAM
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
10 T
OSH2CKLOSC1  to CLKO  —75200ns(1)
11 T
OSH2CKHOSC1  to CLKO  —75200ns(1)
12 T
CKR CLKO Rise Time — 35 100 ns (1)
13 T
CKF CLKO Fall Time — 35 100 ns (1)
14 T
CKL2IOVCLKO  to Port Out Valid — — 0.5 TCY + 20 ns (1)
15 T
IOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns (1)
16 T
CKH2IOI Port In Hold after CLKO  0——ns(1)
17 T
OSH2IOVOSC1  (Q1 cycle) to Port Out Valid — 50 150 ns
18 T
OSH2IOIOSC1  (Q2 cycle) to Port
Input Invalid
(I/O in hold time)
PIC18FXX8X 100 — — ns
18A PIC18LFXX8X 200 — — ns
19 T
IOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns
20 T
IOR Port Output Rise Time PIC18FXX8X — 10 25 ns
20A PIC18LFXX8X — — 60 ns
21 T
IOF Port Output Fall Time PIC18FXX8X — 10 25 ns
21A PIC18LFXX8X — — 60 ns
22† T
INP INT pin High or Low Time TCY ——ns
23† T
RBP RB7:RB4 Change INT High or Low Time TCY ——ns
24† T
RCP RC7:RC4 Change INT High or Low Time 20 ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x T
OSC.
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
ALE
OE
Address
Data from External
166
160
165
161
151
162
163
AD<15:0>
167
168
155
Address
Address
150
A<19:16>
Address
169
BA0
CE
171
171A
164
18F8680.book Page 430 Tuesday, January 29, 2013 1:32 PM