Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 359
PIC18F6585/8585/6680/8680
24.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
®
devices.
The user program memory is divided on binary bound-
aries into four blocks of 16 Kbytes each. The first block
is further divided into a boot block of 2048 bytes and a
second block (Block 0) of 14 Kbytes.
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
FIGURE 24-3: CODE-PROTECTED PROGRAM MEMORY FOR PIC18FXX8X DEVICES
TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
48 Kbytes
(PIC18FX585
64 Kbytes
(PIC18FX680)
Address
Range
Boot Block Boot Block
000000h
0007FFh
CPB, WRTB, EBTRB
Block 0 Block 0
000800h
003FFFh
CP0, WRT0, EBTR0
Block 1 Block 1
004000h
007FFFh
CP1, WRT1, EBTR1
Block 2 Block 2
008000h
00BFFFh
CP2, WRT2, EBTR2
Unimplemented Read ‘0’ Block 3
00C000h
00FFFFh
CP3, WRT3, EBTR3
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L
— — — —CP3
(1)
CP2 CP1 CP0
300009h CONFIG5H CPD CPB
— — — — — —
30000Ah CONFIG6L
— — — —WRT3
(1)
WRT2 WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC
— — — — —
30000Ch CONFIG7L
— — — — EBTR3
(1)
EBTR2 EBTR1 EBTR0
30000Dh CONFIG7H
— EBTRB — — — — — —
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX585 devices.
18F8680.book Page 359 Tuesday, January 29, 2013 1:32 PM