Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 279
PIC18F6585/8585/6680/8680
REGISTER 23-2: CANSTAT: CAN STATUS REGISTER
Mode 0
R-1 R-0 R-0 R-0 R-0 R-0 R-0 U-0
OPMODE2
(1)
OPMODE1
(1)
OPMODE0
(1)
— ICODE2 ICODE1 ICODE0 —
Mode 1, 2
R-1 R-0 R-0 R-0 R-0 R-0 R-0 R-0
OPMODE2
(1)
OPMODE1
(1)
OPMODE0
(1)
EICODE4 EICODE3 EICODE2 EICODE1 EICODE0
bit 7 bit 0
bit 7-5 OPMODE2:OPMODE0: Operation Mode Status bits
(1)
111 = Reserved
110 = Reserved
101 = Reserved
100 = Configuration mode
011 = Listen Only mode
010 = Loopback mode
001 = Disable/Sleep mode
000 = Normal mode
bit 4 Mode 0:
Unimplemented: Read as ‘0’
bit 3-1 ICODE2:ICODE0: Interrupt Code bits in Mode 0
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This
code indicates the source of the interrupt. By copying ICODE2:ICODE0 to WIN2:WIN0, it is pos-
sible to select the correct buffer to map into the Access Bank area. See Example 23-2 for a code
example.
bit 0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
ICODE2:ICODE0 Value
No interrupt 000
Error interrupt 001
TXB2 interrupt 010
TXB1 interrupt 011
TXB0 interrupt 100
RXB1 interrupt 101
RXB0 interrupt 110
Wake-up interrupt 111
18F8680.book Page 279 Tuesday, January 29, 2013 1:32 PM