Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 180  2003-2013 Microchip Technology Inc.
16.2.4 HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin while the complementary PWM
output signal is output on the P1B pin (Figure 16-5).
This mode can be used for half-bridge applications, as
shown in Figure 16-6, or for full-bridge applications
where four power switches are being modulated with
two PWM signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.2.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTE<6> data latches, the
TRISC<2> and TRISE<6> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-5: HALF-BRIDGE PWM
OUTPUT
FIGURE 16-6: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Period
Duty Cycle
td
td
(1)
P1A
(2)
P1B
(2)
td = Dead-band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
PIC18FXX80/XX85
P1A
P1B
FET
Driver
FET
Driver
V+
V-
Load
+
V
-
+
V
-
FET
Driver
FET
Driver
V+
V-
Load
FET
Driver
FET
Driver
PIC18FXX80/XX85
P1A
P1B
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
18F8680.book Page 180 Tuesday, January 29, 2013 1:32 PM