8F8680.book Page 1 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module High-Performance RISC CPU: Analog Features: • Source code compatible with the PIC16 and PIC17 instruction sets • Linear program memory addressing to 2 Mbytes • Linear data memory addressing to 4096 bytes • 1 Kbyte of data EEPROM • Up to 10 MIPs operation: - DC – 40 MHz osc./clock input - 4 MHz-10 MHz osc.
18F8680.book Page 2 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 CMOS Technology: • • • • Low-power, high-speed Flash technology Fully static design Wide operating voltage range (2.0V to 5.
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18F8680.book Page 6 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Oscillator Configurations ............................................................................................................................................................ 23 3.0 Reset ....................
18F8680.book Page 7 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
18F8680.book Page 8 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 8 2003-2013 Microchip Technology Inc.
18F8680.book Page 9 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6585 • PIC18F6680 • PIC18F8585 • PIC18F8680 PIC18F6X8X devices are available in 64-pin TQFP and 68-pin PLCC packages. PIC18F8X8X devices are available in the 80-pin TQFP package. They are differentiated from each other in four ways: 1. 2. 3. 4.
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18F8680.book Page 12 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RG5/MCLR/VPP 7 16 Buffer Type Description ST ST Master Clear (input) or programming voltage (input). General purpose input pin. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input.
18F8680.book Page 13 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 28 34 33 32 31 39 30 27 RA6 38 TTL Analog Digital I/O. Analog input 0.
18F8680.book Page 14 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
18F8680.book Page 15 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTC is a bidirectional I/O port.
18F8680.book Page 16 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled.
18F8680.book Page 17 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTE is a bidirectional I/O port.
F8680.book Page 18 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTF is a bidirectional I/O port.
18F8680.book Page 19 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTG is a bidirectional I/O port. RG0/CANTX1 RG0 CANTX1 3 12 RG1/CANTX2 RG1 CANTX2 4 RG2/CANRX RG2 CANRX 5 RG3 RG3 6 15 8 RG4/P1D RG4 P1D 8 17 10 RG5 7 13 14 16 5 I/O O ST TTL Digital I/O. CAN bus transmit 1.
18F8680.book Page 20 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTH is a bidirectional I/O port(5).
18F8680.book Page 21 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC Pin Type Buffer Type Description TQFP PORTJ is a bidirectional I/O port(5). RJ0/ALE RJ0 ALE — — RJ1/OE RJ1 OE — RJ2/WRL RJ2 WRL — RJ3/WRH RJ3 WRH — RJ4/BA0 RJ4 BA0 — RJ5/CE CE — — 40 RJ6/LB RJ6 LB — — 42 RJ7/UB RJ7 UB — — — — — — 62 I/O O ST TTL Digital I/O.
18F8680.book Page 22 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 22 2003-2013 Microchip Technology Inc.
18F8680.book Page 23 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F6585/8585/6680/8680 devices can be operated in eleven different oscillator modes. The user can program four configuration bits (FOSC3, FOSC2, FOSC1 and FOSC0) to select one of these eleven modes: 1. 2. 3. 4. 5. 6.
18F8680.book Page 24 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Ranges Tested: Mode Freq C1 C2 LP 32.0 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF XT 200 kHz 47-68 pF 47-68 pF 1.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF HS 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 20.0 MHz 15-33 pF 15-33 pF 25.0 MHz TBD TBD These values are for design guidance only. See notes following this table. Crystals Used 32.
18F8680.book Page 25 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.4 External Clock Input 2.5 The EC, ECIO, EC+PLL and EC+SPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is a maximum 1.5 s start-up required after a Power-on Reset, or wake-up from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin.
18F8680.book Page 26 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.6 Oscillator Switching Feature The PIC18F6585/8585/6680/8680 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. For the PIC18F6585/8585/6680/8680 devices, this alternate clock source is the Timer1 oscillator.
18F8680.book Page 27 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.6.1 SYSTEM CLOCK SWITCH BIT The system clock source switching is performed under software control. The System Clock Switch bits, SCS1:SCS0 (OSCCON<1:0>), control the clock switching. When the SCS0 bit is ‘0’, the system clock source comes from the main oscillator that is selected by the FOSC configuration bits in configuration register, CONFIG1H.
18F8680.book Page 28 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.6.2 OSCILLATOR TRANSITIONS The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. In addition to eight clock cycles of the main oscillator, additional delays may take place. PIC18F6585/8585/6680/8680 devices contain circuitry to prevent “glitches” when switching between oscillator sources.
18F8680.book Page 29 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 If the main oscillator is configured for HS mode with PLL active, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur. The PLL timeout is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS-PLL mode, is shown in Figure 2-10.
18F8680.book Page 30 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 If the main oscillator is configured in the RC, RCIO, EC or ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes, is shown in Figure 2-12.
18F8680.book Page 31 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 2.7 Effects of Sleep Mode on the On-Chip Oscillator When the device executes a SLEEP instruction, the onchip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating.
18F8680.book Page 32 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 32 2003-2013 Microchip Technology Inc.
18F8680.book Page 33 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 3.
18F8680.book Page 34 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 3.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, tie the MCLR pin through a 1 k to 10 k resistor to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (i.e.
18F8680.book Page 35 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Oscillator Configuration HS with PLL Brown-out PWRTE = 0 enabled(1) 72 ms + 1024 TOSC + 2ms HS, XT, LP 1024 TOSC + 2 ms 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms + 2ms 1.5 s + 2 ms 2 ms 1.5 s + 2 ms 72 ms + 1024 TOSC 1024 TOSC 1024 TOSC 1024 TOSC 72 ms 1.5 s 1.5 s 1.5 s(3) 72 ms 1.5 s 1.5 s 1.
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18F8680.book Page 50 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD VIA 1 kRESISTOR) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: DS30491D-page 50 TOST = 1024 clock cycles. TPLL 2 ms max.
18F8680.book Page 51 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.0 MEMORY ORGANIZATION There are three memory blocks PIC18F6585/8585/6680/8680 devices. They are: 4.1.1 in • Program Memory • Data RAM • Data EEPROM Data and program memory use separate busses which allows for concurrent access of these blocks. Additional detailed information for Flash program memory and data EEPROM is provided in Section 5.0 “Flash Program Memory” and Section 7.0 “Data EEPROM Memory”, respectively.
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18F8680.book Page 54 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW, or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
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18F8680.book Page 56 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.3 Fast Register Stack 4.4 A “fast interrupt return” option is available for interrupts. A fast register stack is provided for the Status, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt.
18F8680.book Page 57 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.6 Instruction Flow/Pipelining A fetch cycle begins with the program counter (PC) incrementing in Q1. An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining each instruction effectively executes in one cycle.
18F8680.book Page 58 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.7.1 TWO-WORD INSTRUCTIONS The PIC18F6585/8585/6680/8680 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is EXAMPLE 4-3: accessed.
18F8680.book Page 59 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-7 shows the data memory organization for the PIC18F6585/8585/6680/8680 devices. The data memory map is divided into 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed.
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18F8680.book Page 78 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.10 Access Bank 4.11 The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: • • • • • BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read ‘0’s and writes will have no effect.
18F8680.book Page 79 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks.
18F8680.book Page 80 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions.
18F8680.book Page 81 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.13 Status Register The Status register, shown in Register 4-3, contains the arithmetic status of the ALU. The Status register can be the destination for any instruction as with any other register. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
18F8680.book Page 82 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 4.14 RCON Register Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable.
18F8680.book Page 83 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.0 FLASH PROGRAM MEMORY 5.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time.
18F8680.book Page 84 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 5-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 5.2 Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 5.
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18F8680.book Page 86 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.2.2 TABLAT – TABLE LATCH REGISTER 5.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8bit data during data transfers between program memory and data RAM. 5.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory.
18F8680.book Page 87 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.3 Reading the Flash Program Memory TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time.
18F8680.book Page 88 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.4 Erasing Flash Program Memory 5.4.1 The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer or through ICSP control can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1.
18F8680.book Page 89 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.5 Writing to Flash Program Memory The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are eight holding registers used by the table writes for programming.
18F8680.book Page 90 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE 8. 9. 10. 11. 12. The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load table pointer with address being erased. Do the row erase procedure. Load table pointer with address of first byte being written.
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18F8680.book Page 92 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5.5.2 WRITE VERIFY 5.5.4 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 5.5.
18F8680.book Page 93 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.0 Note: EXTERNAL MEMORY INTERFACE The external memory interface is not implemented on PIC18F6X8X (64/68-pin) devices. The external memory interface is a feature of the PIC18F8X8X devices that allows the controller to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program memory. The physical implementation of the interface uses 27 pins.
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18F8680.book Page 95 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports.
18F8680.book Page 96 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.2 16-bit Mode The external memory interface implemented in PIC18F8X8X devices operates only in 16-bit mode. The mode selection is not software configurable but is programmed via the configuration bits. The WM<1:0> bits in the MEMCON register determine three types of connections in 16-bit mode.
18F8680.book Page 97 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.2.2 16-BIT WORD WRITE MODE Figure 6-2 shows an example of 16-bit Word Write mode for PIC18F8X8X devices. FIGURE 6-2: 16-BIT WORD WRITE MODE EXAMPLE PIC18F8X8X AD<7:0> 373 A<20:1> A JEDEC Word EPROM Memory D<15:0> D<15:0> CE AD<15:8> OE WR(1) 373 ALE A<19:16> CE OE WRH Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
18F8680.book Page 98 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.2.3 16-BIT BYTE SELECT MODE Figure 6-3 shows an example of 16-bit Byte Select mode for PIC18F8X8X devices. FIGURE 6-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8X8X AD<7:0> 373 A<20:1> AD<15:8> 373 ALE A<19:16> OE A<20:1> A OE WRH WR(1) WRL BA0 A0 CE CE LB LB UB UB JEDEC Word SRAM Memory D<15:0> D<15:0> Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section 5.
18F8680.book Page 99 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 6.2.4 16-BIT MODE TIMING Figure 6-4 shows the 16-bit mode external bus timing for PIC18F8X8X devices.
18F8680.book Page 100 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 100 2003-2013 Microchip Technology Inc.
18F8680.book Page 101 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 7.0 DATA EEPROM MEMORY 7.1 EEADRH:EEADR The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). The address register pair, EEADRH:EEADR, can address up to a maximum of 1024 bytes of data EEPROM.
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18F8680.book Page 103 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 7.3 Reading the Data EEPROM Memory (EECON1<6>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation).
18F8680.book Page 104 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 7.5 Write Verify 7.7 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory.
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18F8680.book Page 106 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 106 2003-2013 Microchip Technology Inc.
18F8680.book Page 107 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 8.0 8.1 8 x 8 HARDWARE MULTIPLIER 8.2 Introduction An 8 x 8 hardware multiplier is included in the ALU of the PIC18F6585/8585/6680/8680 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored in the 16-bit product register pair (PRODH:PRODL).
18F8680.book Page 108 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
18F8680.book Page 109 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.0 INTERRUPTS The PIC18F6585/8585/6680/8680 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high or a low priority level. The high priority interrupt vector is at 000008h while the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress.
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18F8680.book Page 111 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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18F8680.book Page 114 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Flag registers (PIR1, PIR2 and PIR3).
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18F8680.book Page 117 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must be set to enable any of these peripheral interrupts.
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18F8680.book Page 120 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
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18F8680.book Page 123 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.5 RCON Register The RCON register contains the IPEN bit which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section 4.14 “RCON Register”.
18F8680.book Page 124 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 9.6 INT0 Interrupt 9.7 External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered: either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
18F8680.book Page 125 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.0 I/O PORTS 10.1 Depending on the device selected, there are either seven or nine I/O ports available on PIC18F6X8X/8X8X devices. Some of their pins are multiplexed with one or more alternate functions from the other peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
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18F8680.book Page 127 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-1: PORTA FUNCTIONS Bit# Buffer RA0/AN0 Name bit 0 TTL Input/output or analog input. Function RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF- bit 2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+. RA4/T0CKI bit 4 RA5/AN4/LVDIN bit 5 ST/OD Input/output or external clock input for Timer0. Output is open-drain type.
18F8680.book Page 128 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
18F8680.book Page 129 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch D Q Data Bus I/O pin(1) WR Port CK TRIS Latch D WR TRIS Q TTL Input Buffer CK RD TRIS Q D RD Port EN INTx Schmitt Trigger Buffer Note 1: 2: RD Port I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
18F8680.book Page 130 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-3: PORTB FUNCTIONS Bit# Buffer RB0/INT0 Name bit 0 TTL/ST(1) Input/output pin or external interrupt input 0. Internal software programmable weak pull-up. RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt input 1. Internal software programmable weak pull-up. RB2/INT2 bit 2 TTL/ST(1) Input/output pin or external interrupt input 2. Internal software programmable weak pull-up.
18F8680.book Page 131 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.3 PORTC, TRISC and LATC Registers The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e.
18F8680.book Page 132 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type RC0/T1OSO/T13CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. Function RC1/T1OSI/CCP2(1) bit 1 ST Input/output port pin, Timer1 oscillator input or Capture 2 input/ Compare 2 output/PWM output (when CCP2MX configuration bit is disabled).
18F8680.book Page 133 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin).
18F8680.book Page 134 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE (PIC18F8X8X ONLY) Q D EN EN RD PORTD RD LATD Data Bus D Q Port Data WR LATD or PORTD CK 0 1 I/O pin(1) Data Latch D WR TRISD Q CK TRIS Latch TTL Input Buffer RD TRISD System Bus Control Bus Enable Data/TRIS Out Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS.
18F8680.book Page 135 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-7: PORTD FUNCTIONS Bit# Buffer Type Function RD0/PSP0/AD0(2) Name bit 0 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0. RD1/PSP1/AD1(2) bit 1 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1. (2) bit 2 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2.
18F8680.book Page 136 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin).
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18F8680.book Page 138 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-9: PORTE FUNCTIONS Bit# Buffer Type RE0/RD/AD8(2) Name bit 0 ST/TTL(1) Input/output port pin, read control for Parallel Slave Port or address/data bit 8. For RD (PSP Control mode): 1 = Not a read operation 0 = Read operation, reads PORTD register (if chip selected) Function RE1/WR/AD9(2) bit 1 ST/TTL(1) Input/output port pin, write control for Parallel Slave Port or address/data bit 9.
18F8680.book Page 139 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.6 PORTF, LATF and TRISF Registers EXAMPLE 10-6: PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e.
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18F8680.book Page 141 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-11: PORTF FUNCTIONS Bit# Buffer Type RF0/AN5 Name bit 0 ST Input/output port pin or analog input. RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or comparator 2 output. RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or comparator 1 output. RF3/AN8/C2IN+ bit 3 ST Input/output port pin, analog input or comparator 2 input (+).
18F8680.book Page 142 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.7 PORTG, TRISG and LATG Registers The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. PORTG is a 6-bit wide port with 5 bidirectional pins and 1 unidirectional pin. The corresponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e.
18F8680.book Page 143 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-17: RG1/CANTX2 PIN BLOCK DIAGRAM TX1SRC TXD 0 CANCLK 1 OPMODE2:OPMODE0 = 000 TX2EN ENDRHI 0 VDD RD LATG 1 Data Bus WR PORTG or WR LATG D Q CK Q P Data Latch D Q CK Q I/O pin N WR TRISG TRIS Latch VSS OPMODE2:OPMODE0 = 000 RD TRISG Q Schmitt Trigger D EN RD PORTG Note: I/O pins have diode protection to VDD and VSS.
18F8680.book Page 144 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-20: RG4/P1D PIN BLOCK DIAGRAM CCP1 P1D Enable P1D Out RD LATG Data Bus WR LATG or WR PORTG D CK Data Latch D WR TRISG 1 Q 0 I/O pin Auto-Shutdown Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRISG Q D EN EN RD PORTG Note: I/O pins have diode protection to VDD and VSS.
18F8680.book Page 145 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-13: PORTG FUNCTIONS Bit# Buffer Type RG0/CANTX1 Name bit 0 ST Input/output port pin or CAN bus transmit output. Function RG1/CANTX2 bit 1 ST Input/output port pin, CAN bus complimentary transmit output or CAN bus bit time clock. RG2/CANRX bit 2 ST Input/output port pin or CAN bus receive. RG3 bit 3 ST Input/output port pin. RG4/P1D bit 4 ST Input/output port pin or ECCP1 PWM output D.
18F8680.book Page 146 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.8 Note: PORTH, LATH and TRISH Registers PORTH is available only on PIC18F8X8X devices. FIGURE 10-22: RD LATH PORTH is an 8-bit wide, bidirectional I/O port. The corresponding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode).
18F8680.book Page 147 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-24: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTH RD LATD Data Bus WR LATH or PORTH D Q Port 0 Data 1 CK I/O pin(1) Data Latch D WR TRISH Q CK TRIS Latch TTL Input Buffer RD TRISH External Enable System Bus Control Address Out Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS. 2003-2013 Microchip Technology Inc.
18F8680.book Page 148 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-15: PORTH FUNCTIONS Bit# Buffer Type RH0/A16 Name bit 0 ST/TTL(1) Input/output port pin or address bit 16 for external memory interface. Function RH1/A17 bit 1 ST/TTL(1) Input/output port pin or address bit 17 for external memory interface. RH2/A18 bit 2 ST/TTL(1) Input/output port pin or address bit 18 for external memory interface.
18F8680.book Page 149 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.9 Note: PORTJ, TRISJ and LATJ Registers PORTJ is available only on PIC18F8X8X devices. FIGURE 10-25: RD LATJ PORTJ is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode).
18F8680.book Page 150 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 10-26: RJ5:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTJ RD LATJ Data Bus WR LATJ or PORTJ D Data 0 1 CK I/O pin(1) Data Latch D WR TRISJ Port Q Q CK TRIS Latch RD TRISJ Control Out System Bus Control External Enable Drive System Note 1: I/O pins have diode protection to VDD and VSS.
18F8680.book Page 151 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 10-17: PORTJ FUNCTIONS Bit# Buffer Type RJ0/ALE Name bit 0 ST Input/output port pin or address latch enable control for external memory interface. Function RJ1/OE bit 1 ST Input/output port pin or output enable control for external memory interface. RJ2/WRL bit 2 ST Input/output port pin or write low byte control for external memory interface.
18F8680.book Page 152 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 10.10 Parallel Slave Port (PSP) PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. It is asynchronously readable and writable by the external world through RD control input pin, RE0/RD/AD8 and WR control input pin, RE1/WR/AD9. Note: For PIC18F8X8X devices, the Parallel Slave Port is available only in Microcontroller mode.
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18F8680.book Page 155 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 11.
18F8680.book Page 156 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 0 1 RA4/T0CKI pin Programmable Prescaler 1 Sync with Internal Clocks TMR0 (2 TCY delay) T0SE 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
18F8680.book Page 157 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 11.1 Timer0 Operation 11.2.1 Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler).
18F8680.book Page 158 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 158 2003-2013 Microchip Technology Inc.
18F8680.book Page 159 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 12.0 TIMER1 MODULE Figure 12-1 is a simplified block diagram of the Timer1 module.
18F8680.book Page 160 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 12.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator if enabled. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).
18F8680.book Page 161 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 12.2 Timer1 Oscillator 12.4 A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 200 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. Table 12-1 shows the capacitor selection for the Timer1 oscillator.
18F8680.book Page 162 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 13.0 TIMER2 MODULE 13.
18F8680.book Page 163 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to 0FFh upon Reset.
18F8680.book Page 164 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 14.0 TIMER3 MODULE Figure 14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt on overflow from FFFFh to 0000h • Reset from CCP module trigger REGISTER 14-1: Register 14-1 shows the Timer3 Control register.
18F8680.book Page 165 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled.
18F8680.book Page 166 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated up to 200 kHz. See Section 12.0 “Timer1 Module” for further details. 14.3 The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to 0FFFFh and rolls over to 0000h.
18F8680.book Page 167 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.0 CAPTURE/COMPARE/PWM (CCP) MODULES Additionally, the CCP2 special event trigger may be used to start an A/D conversion if the A/D module is enabled. PIC18FXX80/XX85 devices contain a total of two CCP modules: CCP1 and CCP2. CCP1 is an enhanced version of the CCP2 module. CCP1 is fully backward compatible with the CCP2 module.
18F8680.book Page 168 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 15-2: CCP2CON REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DC2B1:DC2B0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR2L.
18F8680.book Page 169 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.1 CCP Module Both CCP1 and CCP2 are comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte), 1 x 2. The CCPxCON register controls the operation of CCPx. All are readable and writable. An event is selected by control bits CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF (PIR registers), is set. It must be cleared in software.
18F8680.book Page 170 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.2.3 SOFTWARE INTERRUPT 15.2.5 When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCPxIE (PIE registers) clear to avoid false interrupts and should clear the flag bit, CCPxIF, following any such change in operating mode. 15.2.4 CCP PRESCALER There are four prescaler settings specified by bits CCPxM3:CCPxM0.
18F8680.book Page 171 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.3 Compare Mode 15.3.2 The timer used with each CCP module is selected in the T3CCP2:T3CCP1 bits of the T3CON register. Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
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18F8680.book Page 173 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.4 PWM Mode 15.4.1 In Pulse Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. For PWM mode to function properly, the TRIS bit for the CCPx pin must be cleared to make it an output. Note: Clearing the CCPxCON register will force the CCPx PWM output latch to the default low level. This is not the port data latch.
18F8680.book Page 174 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 15.4.3 The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 15-3: 1. F OSC log --------------- F PWM PWM Resolution (max) = -----------------------------bits log 2 2. 3. Note: 5. Set the PWM period by writing to the PR2 register.
18F8680.book Page 175 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The control register for CCP1 is shown in Register 16-1. In addition to the expanded functions of the CCP1CON register, the CCP1 module has two additional registers associated with enhanced PWM operation and auto-shutdown features: The CCP1 module is implemented as a standard CCP module with enhanced PWM capabilities.
18F8680.book Page 176 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.1 ECCP Outputs To configure I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1Mx and CCP1Mx bits (CCP1CON<7:6> and <3:0>, respectively). The appropriate TRIS direction bits for the port pins must also be set as outputs. The enhanced CCP module may have up to four outputs depending on the selected operating mode.
18F8680.book Page 177 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low).
18F8680.book Page 178 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) FIGURE 16-2: 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 16 4 1 1 1 416.67 kHz 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.
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18F8680.book Page 180 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin while the complementary PWM output signal is output on the P1B pin (Figure 16-5). This mode can be used for half-bridge applications, as shown in Figure 16-6, or for full-bridge applications where four power switches are being modulated with two PWM signals.
18F8680.book Page 181 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin PGC is continuously active and pin P1B is modulated. These are illustrated in Figure 16-7.
18F8680.book Page 182 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 16-8: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18FXX80/XX85 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 16.2.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction.
18F8680.book Page 183 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 16-9: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: 2: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
18F8680.book Page 184 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
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18F8680.book Page 186 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.7.1 Auto-Shutdown and Automatic Restart 16.2.8 The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-11), the ECCPASE bit will remain set for as long as the cause of the shutdown continues.
18F8680.book Page 187 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 16.2.9 SETUP FOR PWM OPERATION 7. The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. 8. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRISB bits. Set the PWM period by loading the PR2 register.
18F8680.book Page 188 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 188 2003-2013 Microchip Technology Inc.
18F8680.book Page 189 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
18F8680.book Page 190 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
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18F8680.book Page 192 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
18F8680.book Page 193 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.3 ENABLING SPI I/O 17.3.4 To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
18F8680.book Page 194 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
18F8680.book Page 195 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application.
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18F8680.book Page 197 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.3.8 SLEEP OPERATION 17.3.10 In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/receive data. Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits.
18F8680.book Page 198 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4 I2C Mode 17.4.1 2 The MSSP module in I C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
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18F8680.book Page 202 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation.
18F8680.book Page 203 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given.
DS30491D-page 204 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
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DS30491D-page 206 2 1 4 1 5 0 7 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 A8 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1 Cleared in sof
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18F8680.book Page 208 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.4 CLOCK STRETCHING Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.
18F8680.book Page 209 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line FIGURE 17-12: until an external I2C master device has already asserted the SCL line.
DS30491D-page 210 CKP SSPOV (SSPCON<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs 8
2003-2013 Microchip Technology Inc. UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated 8 9 ACK R/W = 0 SSPBUF is written with contents of SSPSR Cleared in software 2 1 Receive First Byte of Address BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 A7 2 4 5 A3 6 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
18F8680.book Page 212 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master.
18F8680.book Page 213 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
18F8680.book Page 214 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA while SCL outputs the serial clock.
18F8680.book Page 215 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.7 BAUD RATE GENERATOR I2C In Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to ‘0’ and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks.
18F8680.book Page 216 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high.
18F8680.book Page 217 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.8 I2C MASTER MODE START CONDITION TIMING 17.4.8.1 If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a Start condition, the user sets the Start Condition Enable bit, SEN (SSPCON2<0>).
18F8680.book Page 218 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
18F8680.book Page 219 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission.
DS30491D-page 220 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from SSP interrupt 2 D6 Transmitting Dat
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18F8680.book Page 222 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low.
18F8680.book Page 223 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.14 SLEEP OPERATION 17.4.17 I2C While in Sleep mode, the module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 Multi-Master mode support is achieved by bus arbitration.
18F8680.book Page 224 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored.
18F8680.book Page 225 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
18F8680.book Page 226 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.17.2 Bus Collision During a Repeated Start Condition reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs.
18F8680.book Page 227 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to ‘0’. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred.
18F8680.book Page 228 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 228 2003-2013 Microchip Technology Inc.
18F8680.book Page 229 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
18F8680.book Page 230 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC R/W-0 SENDB R/W-0 BRGH R-1 TRMT bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
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18F8680.book Page 232 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode.
18F8680.book Page 233 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.1 USART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the USART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 also control the baud rate.
18F8680.book Page 234 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error 0.3 — — 1.2 — 2.4 9.6 FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — — — 1.221 2.441 1.73 255 9.615 0.16 64 19.2 19.531 1.73 57.6 56.818 115.2 125.000 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — — — 1.73 255 1.202 2.404 0.
18F8680.book Page 235 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error 0.3 0.300 0.00 1.2 1.200 2.4 FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 8332 0.300 0.02 0.02 2082 1.200 2.402 0.06 1040 9.6 9.615 0.16 19.2 19.231 0.16 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 4165 0.300 0.02 -0.03 1041 1.
18F8680.book Page 236 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.1.2 AUTO-BAUD RATE DETECT The enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 18-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging.
18F8680.book Page 237 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.2 USART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the USART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator.
18F8680.book Page 238 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 18-2: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb RC6/TX/CK pin LSb (8) Pin Buffer and Control 0 TSR Register Interrupt Baud Rate CLK TXEN TRMT BRG16 SPBRGH SPEN SPBRG TX9 Baud Rate Generator TX9D FIGURE 18-3: ASYNCHRONOUS TRANSMISSION Write to TXREG BRG Output (Shift Clock) Word 1 RC6/TX/CK (pin) Start bit TRMT bit (Transmit Shift Reg.
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18F8680.book Page 240 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.2.2 USART ASYNCHRONOUS RECEIVER 18.2.3 The receiver block diagram is shown in Figure 18-5. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems.
18F8680.book Page 241 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 5. To set up an asynchronous transmission: 1. 2. 3. 4. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (see Section 18.1 “USART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9.
18F8680.book Page 242 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the USART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the USART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>).
18F8680.book Page 243 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.2.5 BREAK CHARACTER SEQUENCE The enhanced USART module has the capability of sending the special break character sequences that are required by the LIN bus standard. The break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The frame break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data.
18F8680.book Page 244 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.3 USART Synchronous Master Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software.
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18F8680.book Page 246 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.3.2 USART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8.
18F8680.book Page 247 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.4 USART Synchronous Slave Mode To set up a synchronous slave transmission: 1. Synchronous Slave mode is entered by clearing bit CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 18.4.
18F8680.book Page 248 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 18.4.2 USART SYNCHRONOUS SLAVE RECEPTION To set up a synchronous slave reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. 2. 3. 4. 5. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
18F8680.book Page 249 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The module has five registers: The Analog-to-Digital (A/D) converter module has 12 inputs for the PIC18F6X8X devices and 16 inputs for the PIC18F8X8X devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time.
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18F8680.book Page 252 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS) or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF- pins.
18F8680.book Page 253 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 19.
18F8680.book Page 254 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 19.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 19-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD.
18F8680.book Page 255 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 19.3 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
18F8680.book Page 256 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 19.6 A/D Conversions 19.7 Figure 19-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
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18F8680.book Page 259 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 20.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RF1 through RF6 pins. The onchip voltage reference (Section 21.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 20-1: The CMCON register, shown in Register 20-1, controls the comparator input and output multiplexers.
18F8680.book Page 260 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 20.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 20-1 shows the eight possible modes. The TRISF register controls the data direction of the comparator pins for each mode.
18F8680.book Page 261 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 20.2 Comparator Operation 20.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 20-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level.
18F8680.book Page 262 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port pins MULTIPLEX + - CxINV To RF1 or RF2 pin Bus Data Q Read CMCON Set CMIF bit D EN Q From other Comparator D EN CL Read CMCON RESET 20.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator.
18F8680.book Page 263 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 20.7 Comparator Operation During Sleep 20.9 When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. While the comparator is powered up, higher Sleep currents than shown in the power-down current specification will occur.
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18F8680.book Page 265 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 21.0 COMPARATOR VOLTAGE REFERENCE MODULE 21.1 The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference as shown in Register 21-1.
18F8680.book Page 266 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ CVRSS = 0 16 Stages CVRSS = 1 CVREN 8R R R R R CVRR 8R CVRSS = 0 CVRSS = 1 CVREF 16-1 Analog Mux VREFCVR3 (From CVRCON<3:0>) CVR0 Note: R is defined in Section 27.0 “Electrical Characteristics”. 21.2 Voltage Reference Accuracy/Error 21.4 Effects of a Reset The full range of voltage reference cannot be realized due to the construction of the module.
18F8680.book Page 267 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) CVREF Module RF5 + – CVREF Output Voltage Reference Output Impedance Note 1: TABLE 21-1: Name R is dependent upon the voltage reference configuration bits CVRCON<3:0> and CVRCON<5>.
18F8680.book Page 268 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 268 2003-2013 Microchip Technology Inc.
18F8680.book Page 269 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 22.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module.
18F8680.book Page 270 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 22-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD3:LVD0 LVDCON Register 16 to 1 MUX VDD Internally Generated Reference Voltage (Parameter #D423) LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to ‘1111’.
18F8680.book Page 271 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 22.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry.
18F8680.book Page 272 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 22.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods where the voltage is checked.
18F8680.book Page 273 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 22.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module, specified in electrical specification parameter #D423, may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a lowvoltage condition can be reliably detected.
18F8680.book Page 274 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 274 2003-2013 Microchip Technology Inc.
18F8680.book Page 275 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.0 ECAN MODULE PIC18F6585/8585/6680/8680 devices contain an Enhanced Controller Area Network (ECAN) module. The ECAN module is fully backward compatible with the CAN module available in PIC18CXX8 and PIC18FXX8 devices. The Controller Area Network (CAN) module is a serial interface which is useful for communicating with other peripherals or microcontroller devices.
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18F8680.book Page 277 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2 Note: CAN Module Registers Not all CAN registers are available in the Access Bank. There are many control and data registers associated with the CAN module. For convenience, their descriptions have been grouped into the following sections: • • • • • • • 23.2.1 CAN CONTROL AND STATUS REGISTERS The registers described in this section control the overall operation of the CAN module and show its operational status.
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18F8680.book Page 280 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-2: bit 4-0 CANSTAT: CAN STATUS REGISTER (CONTINUED) Mode 1,2: EICODE4:EICODE0: Interrupt Code bits in Mode 1 and Mode 2 When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This code indicates the source of the interrupt. Unlike ICODE bits in Mode 0, these bits may not be copied directly to EWIN bits to map interrupted buffer to Access Bank area.
18F8680.book Page 281 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 23-1: CHANGING TO CONFIGURATION MODE ; Request Configuration mode. MOVLW B’10000000’ ; Set to Configuration Mode. MOVWF CANCON ; A request to switch to Configuration mode may not be immediately honored. ; Module will wait for CAN bus to be idle before switching to Configuration Mode. ; Request for other modes such as Loopback, Disable etc. may be honored immediately.
18F8680.book Page 282 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 23-2: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS (CONTINUED) ErrorInterrupt BCF PIR3, ERRIF ; Clear the interrupt flag … ; Handle error.
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18F8680.book Page 285 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.2 DEDICATED CAN TRANSMIT BUFFER REGISTERS This section describes the dedicated CAN Transmit Buffer registers and their associated control registers.
18F8680.book Page 286 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-6: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 n 2] R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 7-0 bit 0 SID10:SID3: Standard Identifier bits, if EXIDE (TXBnSIDL<3>) = 0; Extended Identifier bits EID28:EID21, if EXIDE = 1.
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18F8680.book Page 289 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 23-3: TRANSMITTING A CAN MESSAGE USING BANKED METHOD ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. And since we want banked method, we need to make sure ; that correct bank is selected.
18F8680.book Page 290 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 EXAMPLE 23-4: TRANSMITTING A CAN MESSAGE USING WIN BITS ; Need to transmit Standard Identifier message 123h using TXB0 buffer. ; To successfully transmit, CAN module must be either in Normal or Loopback mode. ; TXB0 buffer is not in access bank. Use WIN bits to map it to RXB0 area. MOVF CANCON, W ; WIN bits are in lower 4 bits only. Read CANCON ; register to preserve all other bits.
18F8680.book Page 291 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.3 DEDICATED CAN RECEIVE BUFFER REGISTERS This section shows the dedicated CAN Receive Buffer registers with their associated control registers.
18F8680.book Page 292 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-13: RXB0CON: RECEIVE BUFFER 0 CONTROL REGISTER (CONTINUED) bit 2 Mode 0: RXB0DBEN: Receive Buffer 0 Double-Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 Mode 1, 2: FILHIT2: Filter Hit bit 2 This bit combines with other bits to form filter acceptance bits <4:0>.
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18F8680.book Page 294 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-15: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE [0 n 1] R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 7-0 bit 0 SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL<3>); Extended Identifier bits EID28:EID21, if EXID = 1.
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18F8680.book Page 296 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-20: RXBnDm: RECEIVE BUFFER n DATA FIELD BYTE m REGISTERS [0 n 1, 0 m 7] R-x R-x R-x R-x R-x R-x R-x R-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 7-0 bit 0 RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0 n < 1 and 0 < m < 7) Each receive buffer has an array of registers. For example, Receive Buffer 0 has 8 registers: RXB0D0 to RXB0D7.
18F8680.book Page 297 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.3.1 Programmable TX/RX and Auto RTR Buffers The ECAN module contains 6 message buffers that can be programmed as transmit or receive buffers. Any of these buffers can also be programmed to automatically handle RTR messages. Note: These registers are not used in Mode 0.
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18F8680.book Page 299 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-24: BnSIDH: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 7-0 bit 0 SID10:SID3: Standard Identifier bits, if EXIDE (BnSIDL<3>) = 0; Extended Identifier bits EID28:EID21, if EXIDE = 1. Note 1: These registers are available in Mode 1 and 2 only.
18F8680.book Page 300 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-26: BnSIDL: TX/RX BUFFER n STANDARD IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x U-0 R-x R-x SID2 SID1 SID0 SRR EXID — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits, if EXID = 0; Extended Identifier bits EID20:EID18, if EXID = 1.
18F8680.book Page 301 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-28: BnEIDH: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL0) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 7-0 bit 0 EID15:EID8: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only.
18F8680.book Page 302 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-30: BnEIDL: TX/RX BUFFER n EXTENDED IDENTIFIER REGISTERS, LOW BYTE IN RECEIVE MODE [0 n 5, TXnEN (BSEL) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 7-0 bit 0 EID7:EID0: Extended Identifier bits Note 1: These registers are available in Mode 1 and 2 only.
18F8680.book Page 303 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE [0 n 5, 0 m 7, TXnEN (BSEL) = 0](1) R-x R-x R-x R-x R-x R-x R-x R-x BnDm7 BnDm6 BnDm5 BnDm4 BnDm3 BnDm2 BnDm1 BnDm0 bit 7 bit 7-0 bit 0 BnDm7:BnDm0: Receive Buffer n Data Field Byte m bits (where 0 n < 3 and 0 < m < 8) Each receive buffer has an array of registers.
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18F8680.book Page 306 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.3.2 Message Acceptance Filters and Masks This subsection describes the message acceptance filters and masks for the CAN receive buffers. Note: These registers are Configuration mode only.
18F8680.book Page 307 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-39: RXFnEIDH: RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER REGISTERS, HIGH BYTE [0 n 15](1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 7-0 bit 0 EID15:EID8: Extended Identifier Filter bits Note 1: Registers RXF6EIDH:RXF15EIDH are available in Mode 1 and 2 only.
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18F8680.book Page 309 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 23-45: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLC4 FLC3 FLC2 FLC1 FLC0 bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 FLC4:FLC0: Filter Length Count bits Mode 0: Not used; forced to ‘00000’.
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18F8680.book Page 315 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.4 CAN BAUD RATE REGISTERS This subsection describes the CAN Baud Rate registers. Note: These registers are Configuration mode only.
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18F8680.book Page 318 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.5 CAN MODULE I/O CONTROL REGISTER This register controls the operation of the CAN module’s I/O pins in relation to the rest of the microcontroller.
18F8680.book Page 319 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.2.6 CAN INTERRUPT REGISTERS The registers in this section are the same as described in Section 9.0 “Interrupts”. They are duplicated here for convenience.
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18F8680.book Page 328 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.3 CAN Modes of Operation The PIC18F6585/8585/6680/8680 has six main modes of operation: • • • • • • Configuration mode Disable mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode All modes, except Error Recognition, are requested by setting the REQOP bits (CANCON<7:5>); Error Recognition is requested through the RXM bits of the Receive Buffer register(s).
18F8680.book Page 329 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.3.3 NORMAL MODE 23.3.6 ERROR RECOGNITION MODE This is the standard operating mode of the PIC18F6585/8585/6680/8680 devices. In this mode, the device actively monitors all bus messages and generates Acknowledge bits, error frames, etc. This is also the only mode in which the PIC18F6585/8585/6680/ 8680 devices will transmit messages over the CAN bus. The module can be set to ignore all errors and receive any message.
18F8680.book Page 330 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 When a receive buffer is programmed to use standard identifier messages, part of the full Acceptance Filter register can be used as data byte filter. The length of data byte filter is programmable from 0 to 18 bits. This functionality simplifies implementation of high-level protocols, such as DeviceNet.
18F8680.book Page 331 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.5.3 PROGRAMMABLE TRANSMIT/ RECEIVE BUFFERS The ECAN module implements six new buffers: B0-B5. These buffers are individually programmable as either transmit or receive buffers. These buffers are available only in Mode 1 and 2. As with dedicated transmit and receive buffers, each of these programmable buffers occupies 14 bytes of SRAM and are mapped into SFR memory map.
18F8680.book Page 332 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 ABORTING TRANSMISSION Once an abort is requested by setting ABAT or TXABT bits, it cannot be cleared to cancel the abort request. Only CAN module hardware or a POR condition can clear it. The MCU can request to abort a message by clearing the TXREQ bit associated with the corresponding message buffer (TXBnCON<3> or BnCON<3>). Setting the ABAT bit (CANCON<4>) will request an abort of all pending messages.
18F8680.book Page 333 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.7 23.7.1 Message Reception RECEIVING A MESSAGE Of all receive buffers, the MAB is always committed to receiving the next message from the bus. The MCU can access one buffer while the other buffer is available for message reception, or holding a previously received message. Note: The entire contents of the MAB are moved into the receive buffer once a message is accepted.
18F8680.book Page 334 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 In Mode 1 and 2, there are a total of 16 acceptance filters available and each can be dynamically assigned to any of the receive buffers. A buffer with a lower number has higher priority. Given this, if an incoming message matches with two or more receive buffer acceptance criteria, the buffer with the lower number will be loaded with that message. 23.7.4 23.7.
18F8680.book Page 335 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 In Mode 1 and 2, there are an additional 10 acceptance filters, RXF6-RXF15, creating a total of 16 available filters. RXF15 can be used either as an acceptance filter or acceptance mask register. Each of these acceptance filters can be individually enabled or disabled by setting or clearing RXFENn bit in the RXFCONn register. Any of these 16 acceptance filters can be dynamically associated with any of the receive buffers.
18F8680.book Page 336 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.9 Baud Rate Setting All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Returnto-Zero (NRZ) coding which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitter’s clock.
18F8680.book Page 337 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.9.1 TIME QUANTA 23.9.2 SYNCHRONIZATION SEGMENT As already mentioned, the Time Quanta is a fixed unit derived from the oscillator period and baud rate prescaler. Its relationship to TBIT and the Nominal Bit Rate is shown in Example 23-6. This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ.
18F8680.book Page 338 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.10 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync_Seg).
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18F8680.book Page 340 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.11 Programming Time Segments 23.13.2 Some requirements for programming of the time segments: The PRSEG bits set the length of the propagation segment in terms of TQ. The SEG1PH bits set the length of Phase Segment 1 in TQ. The SAM bit controls how many times the RXCAN pin is sampled.
18F8680.book Page 341 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.14.2 ACKNOWLEDGE ERROR In the Acknowledge field of a message, the transmitter checks if the Acknowledge slot (which was sent out as a recessive bit) contains a dominant bit. If not, no other node has received the frame correctly. An Acknowledge error has occurred; an error frame is generated and the message will have to be repeated. 23.14.
18F8680.book Page 342 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 23-7: ERROR MODES STATE DIAGRAM Reset ErrorActive RXERRCNT < 127 or TXERRCNT < 127 RXERRCNT > 127 or TXERRCNT > 127 128 occurrences of 11 consecutive “recessive” bits ErrorPassive TXERRCNT > 255 BusOff 23.15 CAN Interrupts The transmit related interrupts are: The module has several sources of interrupts. Each of these interrupts can be individually enabled or disabled.
18F8680.book Page 343 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 23.15.2 TRANSMIT INTERRUPT When the transmit interrupt is enabled, an interrupt will be generated when the associated transmit buffer becomes empty and is ready to be loaded with a new message. In Mode 0, there are separate interrupt enable/disable and flag bits for each of the three dedicated transmit buffers. The TXBnIF bit will be set to indicate the source of the interrupt.
18F8680.book Page 344 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 344 2003-2013 Microchip Technology Inc.
18F8680.book Page 345 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.0 SPECIAL FEATURES OF THE CPU There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
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18F8680.book Page 348 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.
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18F8680.book Page 351 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2 CP1 CP0 bit 7 bit 7-4 bit 3 bit 2 bit 1 bit 0 bit 0 Unimplemented: Read as ‘0’ CP3: Code Protection bit(1) 1 = Block 3 (00C000-00FFFFh) not code-protected 0 = Block 3 (00C000-00FFFFh) code-protected Note 1: Unimplemented in PIC18FX585 devices; maintain this bit set.
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18F8680.book Page 354 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 REGISTER 24-13: DEVICE ID REGISTER 1 FOR PIC18FXX8X DEVICES (ADDRESS 3FFFFEh) R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F8680 001 = PIC18F6680 010 = PIC18F8585 011 = PIC18F6585 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision.
18F8680.book Page 355 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.2 Watchdog Timer (WDT) The Watchdog Timer is a free-running, on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run even if the clock on the OSC1/CLKI and OSC2/CLKO/RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction.
18F8680.book Page 356 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming by the value written to the CONFIG2H Configuration register. FIGURE 24-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 16 WDTPS3:WDTPS0 16-to-1 MUX WDTEN Configuration bit SWDTEN bit WDT Time-out Note: TABLE 24-2: WDPS3:WDPS0 are bits in register CONFIG2H.
18F8680.book Page 357 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.3 Power-down Mode (Sleep) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (RCON<3>) is cleared, the TO (RCON<4>) bit is set and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or high-impedance).
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18F8680.book Page 359 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.4 Program Verification and Code Protection Figure 24-3 shows the program memory organization for 48 and 64-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 24-3. The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® devices.
18F8680.book Page 360 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.4.1 PROGRAM MEMORY CODE PROTECTION The user memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. that block is not allowed to read and will result in reading ‘0’s.
18F8680.book Page 361 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 24-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 000FFFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 003FFFh 004000h PC = 004FFEh TBLRD * WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0.
18F8680.book Page 362 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.4.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 24.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
18F8680.book Page 363 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 24.8 Low-Voltage ICSP Programming The LVP bit in Configuration register, CONFIG4L, enables Low-Voltage ICSP Programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH but can instead be left at the normal operating voltage.
18F8680.book Page 364 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 364 2003-2013 Microchip Technology Inc.
18F8680.book Page 365 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 25.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PIC MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits) but there are three instructions that require two program memory locations.
18F8680.book Page 366 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank.
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18F8680.book Page 371 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 25.1 Instruction Set ADDLW ADD literal to W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: 1111 kkkk kkkk The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
18F8680.book Page 372 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 ADDWFC ADD W and Carry bit to f Syntax: [ label ] ADDWFC Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a]] Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 1 Cycles: 1 AND literal with W Syntax: [ label ] ANDLW Operands: 0 k 255 Operation: (W) .AND.
18F8680.book Page 373 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a]] BC Branch if Carry Syntax: [ label ] BC Operands: -128 n 127 Operation: if carry bit is ‘1’ (PC) + 2 + 2n PC None Operation: (W) .AND.
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18F8680.book Page 377 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BRA Unconditional Branch Syntax: [ label ] BRA Operands: -1024 n 1023 n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 1 Cycles: 2 Q Cycle Activity: Q1 No operation nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction.
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18F8680.book Page 381 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Clears the contents of the specified register.
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18F8680.book Page 386 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 GOTO Unconditional Branch Syntax: [ label ] Operands: 0 k 1048575 Operation: k PC<20:1> Status Affected: None Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value ‘k’ is loaded into PC<20:1>. GOTO is always a two-cycle instruction.
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18F8680.book Page 388 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 IORLW Inclusive OR literal with W Syntax: [ label ] Operands: 0 k 255 Operation: (W) .OR. k W Status Affected: N, Z Encoding: 0000 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: kkkk kkkk Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W IORLW Before Instruction = 0x9A After Instruction W 1001 The contents of W are OR’ed with the eight-bit literal ‘k’.
18F8680.book Page 389 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 LFSR Load FSR Syntax: [ label ] Operands: 0f2 0 k 4095 Operation: k FSRf Status Affected: None Encoding: Description: 1110 1111 LFSR f,k 1110 0000 00ff k7kkk k11kkk kkkk The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
18F8680.book Page 390 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] Syntax: [ label ] Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.
18F8680.book Page 391 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 MOVLW Move literal to W Syntax: [ label ] Operands: 0 k 255 Operation: kW Status Affected: None Encoding: 0000 Description: MOVLW k 1110 Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: kkkk Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W MOVLW 0x5A After Instruction W kkkk The eight-bit literal ‘k’ is loaded into W.
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18F8680.book Page 393 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NEGF Negate f Syntax: [ label ] 0 f 255 a [0,1] Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: ffff 1 Cycles: 1 Q Cycle Activity: Q1 [ label ] None Operation: No operation Status Affected: None 0000 1111 Description: 1 Cycles: 1 Decode 0000 xxxx 0000 xxxx 0000 xxxx No operation.
18F8680.book Page 394 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 POP Pop Top of Return Stack Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC+2) TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded.
18F8680.book Page 395 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RCALL Relative Call Reset Syntax: [ label ] RCALL Syntax: [ label ] Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 nnnn nnnn Subroutine call with a jump up to 1K from the current location.
18F8680.book Page 396 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RETFIE Return from Interrupt Return Literal to W Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged.
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18F8680.book Page 399 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RRNCF Rotate Right f (no carry) Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<0>) dest<7> Status Affected: N, Z Encoding: 0100 Description:’ RRNCF f [,d [,a]] 1 1 [ label ] SETF 0 f 255 a [0,1] Operation: FFh f Status Affected: None 0110 00da ffff 100a ffff ffff The contents of the specified register are set to FFh.
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18F8680.book Page 405 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: skip if f = 0 Status Affected: None Encoding: 0110 Description: ffff ffff Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Decode (W) .XOR.
18F8680.book Page 406 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default).
18F8680.book Page 407 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.
18F8680.book Page 408 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers.
18F8680.book Page 409 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers.
18F8680.book Page 410 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.14 PICSTART Plus Development Programmer 26.17 PICDEM 2 Plus Demonstration Board The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PIC devices up to 40 pins.
18F8680.book Page 411 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 26.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development.
18F8680.book Page 412 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 412 2003-2013 Microchip Technology Inc.
18F8680.book Page 413 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature ..............................................................................................................................
18F8680.book Page 414 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-1: PIC18F6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18FXX8X Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V Frequency FMAX FMAX = 40 MHz for PIC18F6X8X and PIC18F8X8X in Microcontroller mode. FMAX = 25 MHz for PIC18F8X8X in modes other than Microcontroller mode. FIGURE 27-2: PIC18LF6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LFXX8X 4.
18F8680.book Page 415 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-3: PIC18F6585/8585/6680/8680 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18FXX8X 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz Frequency 2003-2013 Microchip Technology Inc.
18F8680.book Page 416 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.1 DC Characteristics: Supply Voltage PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) PIC18LFXX8X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18FXX8X (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param.
18F8680.book Page 417 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.
18F8680.book Page 418 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.
18F8680.book Page 419 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.
18F8680.book Page 420 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.
18F8680.book Page 421 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.3 DC Characteristics: PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V VDD 5.5V VSS VSS 0.2 VDD 0.
18F8680.book Page 422 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.3 DC Characteristics: PIC18FXX8X (Industrial, Extended) PIC18LFXX8X (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic D080A OSC2/CLKO (RC mode) D083A VOH D090 D090A OSC2/CLKO (RC mode) D092A D150 VOD Units Conditions — 0.
18F8680.book Page 423 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated Param No. Sym Characteristics Min Typ Max Units mV D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 D301 VICM Input Common Mode Voltage 0 — VDD – 1.
18F8680.book Page 424 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-4: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 27-3: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param Symbol No.
18F8680.book Page 425 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-4: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC Characteristics Param No. Sym Characteristic Min Typ† Max Units Conditions Internal Program Memory Programming Specifications (Note 1) D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.
18F8680.book Page 426 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.4 27.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
18F8680.book Page 427 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 27-5 apply to all timing specifications unless otherwise noted. Figure 27-5 specifies the load conditions for the timing specifications.
18F8680.book Page 428 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKO TABLE 27-6: Param. No.
18F8680.book Page 429 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-7: Param. No. Sym PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) Characteristic Min Typ† Max Units Conditions — FOSC Oscillator Frequency Range 4 — 10 MHz HS mode — FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode — trc PLL Start-up Time (Lock Time) — — 2 ms — CLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25C, unless otherwise stated.
18F8680.book Page 430 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-8: Param. No. CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions 10 TOSH2CKL OSC1 to CLKO — 75 200 ns (1) 11 TOSH2CKH OSC1 to CLKO — 75 200 ns (1) 12 TCKR CLKO Rise Time — 35 100 ns (1) 13 TCKF CLKO Fall Time — 35 100 ns (1) 14 TCKL2IOV CLKO to Port Out Valid — — 0.5 TCY + 20 ns (1) 15 TIOV2CKH Port In Valid before CLKO 0.
18F8680.book Page 431 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-9: Param. No PROGRAM MEMORY READ TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V) Symbol Characteristics Min Typ Max Units 0.25 TCY – 10 — — ns — ns 150 TADV2ALL Address Out Valid to ALE (address setup time) 151 TALL2ADL ALE to Address Out Invalid (address hold time) 5 — 155 TALL2OEL ALE to OE 10 0.
18F8680.book Page 432 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V) Param. No. Symbol Characteristics Min Typ Max Units 150 TADV2ALL Address Out Valid to ALE (address setup time) 0.
18F8680.book Page 433 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-11: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. No.
18F8680.book Page 434 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param. No. 40 Symbol TT0H Characteristic T0CKI High Pulse Width No prescaler With prescaler 41 TT0L T0CKI Low Pulse Width No prescaler With prescaler 42 TT0P T0CKI Period No prescaler With prescaler 45 TT1H T1CKI Synchronous, no prescaler High Time Synchronous, PIC18FXX8X with prescaler PIC18LFXX8X Asynchronous 46 TT1L 47 0.
18F8680.book Page 435 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-13: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 27-5 for load conditions. TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol No. 50 51 TCCL TCCH Characteristic Min CCPx Input Low No prescaler Time With PIC18FXX8X prescaler PIC18LFXX8X 0.
18F8680.book Page 436 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-14: PARALLEL SLAVE PORT TIMING (PIC18FXX8X) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 27-5 for load conditions. TABLE 27-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18FXX8X) Param. No. Symbol Characteristic Min Max Units Conditions 20 25 — — ns ns Extended Temp.
18F8680.book Page 437 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-15: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 27-5 for load conditions. TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. No.
18F8680.book Page 438 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-16: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO LSb bit 6 - - - - - -1 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 Note: Refer to Figure 27-5 for load conditions. TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. Symbol Min Max Units SCK Input High Time (Slave mode) Continuous 1.
18F8680.book Page 439 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-17: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 27-5 for load conditions. TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param. No.
18F8680.book Page 440 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-18: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 bit 6 - - - -1 LSb In 74 Note: Refer to Figure 27-5 for load conditions. TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. No.
18F8680.book Page 441 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-19: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-5 for load conditions. TABLE 27-19: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
18F8680.book Page 442 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-20: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH Characteristic Clock High Time Min Max Units Conditions 100 kHz mode 4.0 — s PIC18FXX8X must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18FXX8X must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — s PIC18FXX8X must operate at a minimum of 1.5 MHz 400 kHz mode 1.
18F8680.book Page 443 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-21: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-5 for load conditions. TABLE 27-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
18F8680.book Page 444 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-22: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol No.
18F8680.book Page 445 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-23: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 27-5 for load conditions. TABLE 27-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No.
18F8680.book Page 446 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TABLE 27-25: A/D CONVERTER CHARACTERISTICS: PIC18F6585/8585/6680/8680 (INDUSTRIAL, EXTENDED) PIC18LF6585/8585/6680/8680 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units bit bit Conditions VREF = VDD 3.0V VREF = VDD 3.0V A01 NR Resolution — — — — 10 TBD A03 EIL Integral Linearity Error — — — — <±1 TBD LSb VREF = VDD 3.0V LSb VREF = VDD 3.
18F8680.book Page 447 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 27-25: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
18F8680.book Page 448 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 448 2003-2013 Microchip Technology Inc.
18F8680.book Page 449 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 28.0 Note: DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g.
18F8680.book Page 450 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 40 36 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 32 28 5.5V IDD (mA) 24 5.0V 20 4.5V 4.2V 16 12 8 4 0 4 5 6 7 8 9 10 9 10 FOSC (MHz) MAXIMUM IDD vs.
18F8680.book Page 451 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 5 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 4 5.0V 4.5V 4.0V 3 IDD (mA) 3.5V 3.0V 2 2.5V 2.0V 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 FOSC (MHz) MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) FIGURE 28-6: 7 5.
18F8680.book Page 452 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 1 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.9 5.5V 0.8 5.0V 4.5V IDD (mA) 0.7 4.0V 0.6 3.5V 0.5 3.0V 2.5V 0.4 2.0V 0.3 0.2 20 30 40 50 60 70 80 90 100 80 90 100 FOSC (kHz) MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) FIGURE 28-8: 6 5.
18F8680.book Page 453 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-9: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 40 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 36 5.5V 32 5.0V 28 4.5V 4.2V IDD (mA) 24 4.0V 20 16 3.5V 12 3.0V 8 4 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) MAXIMUM IDD vs.
18F8680.book Page 454 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-11: TYPICAL AND MAXIMUM IT1OSC vs. VDD (TIMER1 AS SYSTEM CLOCK) 240 Typical: statistical mean @ 25°C Maximum: mean + 3 (-10°C to +70°C) Minimum: mean – 3 (-10°C to +70°C) 220 200 180 160 IDD (uA) 140 120 100 80 Max (70°C) 60 Typ (25°C) 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-12: AVERAGE FOSC vs.
18F8680.book Page 455 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-13: AVERAGE FOSC vs. VDD FOR VARIOUS R’s (RC MODE, C = 100 pF, TEMP = 25°C) 2,200 2,000 1,800 3.3 k 3.3k 1,600 Freq (kHz) 1,400 5.1 k 5.1k 1,200 1,000 800 10 k 10k 600 400 200 100 k 100k 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-14: AVERAGE FOSC vs. VDD FOR VARIOUS R’s (RC MODE, C = 300 pF, TEMP = 25°C) 800 700 3.3 k 3.3k 600 Freq (MHz) 500 5.1 k 5.
18F8680.book Page 456 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-15: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 1000 Max (-40°C to +125°C) 100 Max (85°C) IPD (uA) 10 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1 Typ (25°C) 0.1 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-16: TYPICAL AND MAXIMUM IBOR vs. VDD OVER TEMPERATURE, VBOR = 2.00V-2.
18F8680.book Page 457 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-17: IT1OSC vs. VDD (SLEEP MODE, TIMER1 AND OSCILLATOR ENABLED) 80 Typical: statistical mean @ 25°C Maximum: mean + 3 (-10°C to +70°C) Minimum: mean – 3 (-10°C to +70°C) 70 Max (70°C) 60 IPD (uA) 50 40 30 20 Typ (25°C) 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-18: IPD vs.
18F8680.book Page 458 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-19: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD 40 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 35 Max (125°C) 30 WDT Period (ms) Max (85°C) 25 20 Typ (25°C) 15 Min (-40°C) 10 5 0 2.5 3.0 FIGURE 28-20: 3.5 4.0 VDD (V) 4.5 5.0 5.5 ILVD vs. VDD OVER TEMPERATURE, VLVD = 4.5-4.
18F8680.book Page 459 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.5 5.0 4.5 Max Max 4.0 Typ Typ(+25°C) (25C) VOH (V) 3.5 3.0 Min Min 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 28-22: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.0 2.5 2.0 VOH (V) Max Max 1.5 Typ Typ(+25°C) (25C) 1.0 Min Min 0.5 0.
18F8680.book Page 460 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1.8 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.4 VOL (V) 1.2 1.0 Max Max 0.8 0.6 0.4 Typ (+25°C) Typ (25C) 0.2 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 28-24: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 2.
18F8680.book Page 461 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-25: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 3.5 VIH Max 3.0 2.5 VIN (V) VIH Min 2.0 VIL Max 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-26: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C) 1.
18F8680.book Page 462 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C) FIGURE 28-27: 3.5 VIH Max Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 3.0 2.5 2.0 VIN (V) VVILILMax VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) FIGURE 28-28: 4 3.
18F8680.book Page 463 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 FIGURE 28-29: A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) 2003-2013 Microchip Technology Inc.
18F8680.book Page 464 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 464 2003-2013 Microchip Technology Inc.
18F8680.book Page 465 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F6680 -I/PT 0410017 68-Lead PLCC Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
18F8680.book Page 466 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 29.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
18F8680.book Page 467 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 68-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D CH2 x 45 n12 CH1 x 45 A3 A2 32 A c B1 p B A1 D2 E2 Units Dimension Limits n p MIN INCHES* NOM 68 .050 17 .173 .153 .028 .029 .045 .005 .990 .990 .954 .954 .920 .920 .011 .029 .
18F8680.book Page 468 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
18F8680.book Page 469 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 APPENDIX A: REVISION HISTORY Revision A (February 2003) Original data sheet for PIC18F6585/8585/6680/8680 family. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (June 2003) This revision includes updates to the Special Function Registers in Table 4-2 and Table 23-1 and minor corrections to the data sheet text.
18F8680.book Page 470 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC17C756 to a PIC18F8720.
18F8680.book Page 471 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration.” This Application Note is available as Literature Number DS00726. 2003-2013 Microchip Technology Inc.
18F8680.book Page 472 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 472 2003-2013 Microchip Technology Inc.
18F8680.book Page 473 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 INDEX A A/D .................................................................................... 249 A/D Converter Interrupt, Configuring ....................................................... 253 Acquisition Requirements ......................................... 254 Acquisition Time........................................................ 254 ADCON0 Register.....................................................
18F8680.book Page 474 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 PORTD in I/O Port Mode .......................................... 133 PORTD in System Bus Mode ................................... 134 PORTE in I/O Mode .................................................. 137 PORTE in System Bus Mode.................................... 137 PORTF RF1/AN6/C2OUT and RF2/AN7/C1OUT Pins .............................. 139 RF6:RF3 and RF0 Pins..................................... 140 RF7 Pin ........
18F8680.book Page 475 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Saving Status, WREG and BSR Registers in RAM .............................................................. 124 Transmitting a CAN Message Using Banked Method................................................. 289 Transmitting a CAN Message Using WIN Bits ............................................................ 290 WIN and ICODE Bits Usage in Interrupt Service Routine to Access TX/RX Buffers ................................
18F8680.book Page 476 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 E ECAN Module ................................................................... 275 Baud Rate Setting ..................................................... 337 Bit Time Partitioning .................................................. 337 Bit Timing Configuration Registers........................................................... 340 Calculating TQ, Nominal Bit Rate and Nominal Bit Time.......................................
18F8680.book Page 477 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 F Firmware Instructions........................................................ 365 Flash Program Memory ...................................................... 83 Associated Registers .................................................. 92 Control Registers ........................................................ 84 Erase Sequence ......................................................... 88 Erasing..............................
18F8680.book Page 478 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 SLEEP ...................................................................... 400 SUBFWP................................................................... 400 SUBLW ..................................................................... 401 SUBWF ..................................................................... 401 SUBWFB................................................................... 402 SWAPF ..........................
18F8680.book Page 479 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Master Mode ..................................................... 213 Reception.................................................. 219 Repeated Start Condition Timing ............................................... 218 Transmission ............................................ 219 Master Mode Start Condition ............................ 217 Module Operation .............................................
18F8680.book Page 480 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 RE2/CS/AD10 ............................................................. 17 RE3/AD11 ................................................................... 17 RE4/AD12 ................................................................... 17 RE5/AD13/P1C ........................................................... 17 RE6/AD14/P1B ........................................................... 17 RE7/CCP2/AD15 ..........................
18F8680.book Page 481 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Product Identification System ........................................... 487 Program Counter PCL, PCLATH and PCLATU Registers............................................................. 56 Program Memory Instructions.................................................................. 57 Two-Word ........................................................... 58 Interrupt Vector ....................................................
18F8680.book Page 482 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 BnSIDL (TX/RX Buffer n Standard Identifier, Low Byte in Transmit Mode)................................................. 300 BRGCON1 (Baud Rate Control 1) ............................ 315 BRGCON2 (Baud Rate Control 2) ............................ 316 BRGCON3 (Baud Rate Control 3) ............................ 317 BSEL0 (Buffer Select 0) ............................................ 305 CANCON (CAN Control) ......................
18F8680.book Page 483 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 TXBIE (Transmit Buffers Interrupt Enable) ............................................... 322 TXBnCON (Transmit Buffer n Control) ............................................................. 285 TXBnDLC (Transmit Buffer n Data Length Code) ........................................... 288 TXBnDm (Transmit Buffer n Data Field Byte m) ............................................
18F8680.book Page 484 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 Timer2 ............................................................................... 162 Associated Registers ................................................ 163 Operation .................................................................. 162 Postscaler. See Postscaler, Timer2. PR2 Register............................................. 162, 173, 177 Prescaler. See Prescaler, Timer2. SSP Clock Shift..........................
18F8680.book Page 485 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 SPI Mode (Slave Mode with CKE = 1) ........................................................... 196 Stop Condition Receive or Transmit Mode .................................................. 222 Synchronous Reception (Master Mode, SREN) ...................................... 246 Synchronous Transmission....................................... 244 Synchronous Transmission (Through TXEN) ..........................................
18F8680.book Page 486 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 486 2003-2013 Microchip Technology Inc.
18F8680.book Page 487 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
18F8680.book Page 488 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
18F8680.book Page 489 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 PIC18F6585/8585/6680/8680 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. – Device Device X Temperature Range /XX XXX Package Pattern PIC18FXX8X(1), PIC18FXX8XT(2); VDD range 4.2V to 5.5V PIC18LFXX8X(1), PIC18LFXX8XT(2); VDD range 2.0V to 5.
18F8680.book Page 490 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 490 2003-2013 Microchip Technology Inc.
18F8680.book Page 491 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: 2003-2013 Microchip Technology Inc.
18F8680.book Page 492 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: DS30491D-page 492 2003-2013 Microchip Technology Inc.
18F8680.book Page 493 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 NOTES: 2003-2013 Microchip Technology Inc.
18F8680.book Page 494 Tuesday, January 29, 2013 1:32 PM PIC18F6585/8585/6680/8680 DS30491D-page 494 2003-2013 Microchip Technology Inc.
18F8680.book Page 495 Tuesday, January 29, 2013 1:32 PM Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
18F8680.book Page 496 Tuesday, January 29, 2013 1:32 PM Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.
