Datasheet

PIC18F6527/6622/8527/8622
DS80253B-page 6 © 2006 Microchip Technology Inc.
22. Module: Reset
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 28.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
occurs when a write operation is being
executed (start of a Q4 cycle).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
23. Module: External Memory Bus
The A<19:16> EMB address lines and Read/Write
control pins (OE
, WRH and WRL) are released to
their respective inactive states at the same time,
violating the timing condition mentioned in
Figure 28-8 and Figure 28-9 in the Device Data
Sheet. This may result in a peripheral device on
the bus detecting an address change when a write/
read is initiated. The bus capacitance and signal
delay on the address and control lines can affect
the probability of invalid detection.
Work around
Two work arounds are available:
1. Use a latch based on the falling edge of ALE to
hold the A<19:16> signals.
2. Add a delay circuit to extend the valid time for
A<19:16> signals to ensure the address is
valid until read/write signals go inactive.