Datasheet

© 2006 Microchip Technology Inc. DS80253B-page 5
PIC18F6527/6622/8527/8622
17. Module: MSSP (I
2
C Mode)
It has been observed that, following a Power-on
Reset, I
2
C mode may not initialize properly by just
configuring the SCLx and SDAx pins as either
inputs or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application's power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
2
C operation:
1. Configure the SCLx and SDAx pins as outputs
by clearing their corresponding TRIS bits.
2. Force SCLx and SDAx low by clearing the
corresponding LAT bits.
3. While keeping the LAT bits clear, configure
SCLx and SDAx as inputs by setting their TRIS
bits.
Once this is done, use the SSPxCON1 and
SSPxCON2 registers to configure the proper I
2
C
mode as before.
Date Codes that pertain to this issue:
All engineering and production devices.
18. Module: MSSP (I
2
C Mode)
In I
2
C Master mode, the RCEN bit is set by soft-
ware to begin data reception, and cleared by the
peripheral after a byte is received. After a byte is
received, the device may take up to 80 T
CY to clear
RCEN and 800 T
CY during emulation.
Work around
Single byte receptions are typically not affected,
since the delay between byte receptions typically
is long enough for the RCEN bit to clear. For mul-
tiple byte receptions, the software must wait until
the bit is cleared by the peripheral before the next
byte can be received.
Date Codes that pertain to this issue:
All engineering and production devices.
19. Module: ECCP (PWM Mode)
When the PWM auto-shutdown feature is
configured for automatic restart by setting the
PxRSEN bit (ECCPxDEL<7>), the pulse may ter-
minate immediately in a shutdown event. In addi-
tion, the pulse may restart within the period if the
shutdown condition expires. This may result in the
generation of short pulses on the PWM output(s).
Work around
Configure the auto-shutdown for software restart
by clearing the PxRSEN bit. The PWM can be re-
enabled by clearing the ECCPxASE bit
(ECCPxAS<7>) after the shutdown condition
expires.
Date Codes that pertain to this issue:
All engineering and production devices.
20. Module: ECCP (PWM Mode)
When configured for half-bridge operation with
dead band (CCPxCON<7:6> = 10), the PWM out-
put may be corrupted for certain values of the
PWM duty cycle. This can occur when these
additional criteria are also met:
• a non-zero, dead-band delay is specified
(PxDC6:PxDC0 > 0); and
• the duty cycle has a value of 0 through 3, or
4n + 3 (n ≥ 1).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
21. Module: CCP (PWM Mode)
Timer4 is not available as a clock source for either
CCP4 or CCP5 in any PWM mode
(CCPxCON<3:2> = 11). Selecting Timer4 as the
module’s clock source may cause the PWM output
to stop generating pulses.
Work around
To use CCP4 or CCP5 in PWM mode, use only
Timer2 as the clock source (T3CON<6,3> = 00).
Date Codes that pertain to this issue:
All engineering and production devices.