Datasheet

PIC18F6527/6622/8527/8622
DS80253B-page 4 © 2006 Microchip Technology Inc.
14. Module: MSSP (SPI Mode)
In SPI mode, the Buffer Full Status bit, BF
(SSPxSTAT<0>), should not be polled in software
to determine when the transfer is complete.
Work around
Copy the SSPxSTAT register into a variable and
perform the bit test on the variable. In Example 1,
SSPxSTAT is copied into the working register
where the bit test is performed (SSP1STAT is
shown, but this process is also applicable to
SSP2STAT).
EXAMPLE 1:
A second option is to poll the appropriate Master
Synchronous Serial Port Interrupt Flag bit,
SSPxIF. This bit can be polled and will set when
the transfer is complete.
Date Codes that pertain to this issue:
All engineering and production devices.
15. Module: MSSP (SPI Mode)
In SPI Master mode, a write collision may occur if
the SSPxBUF register is loaded immediately after
a transfer is complete. This may be caused by an
inadequate delay between the MSSP Interrupt
Flag bit (SSPxIF) or the Buffer Full bit (BF) being
set, and SSPxBUF being written to.
This has only been observed when the SPI clock
is operating at F
OSC/64 or ((Timer2)/2)
(SSPxCON1<3:0> = 001x).
Work around
Add a software delay of one SCKx period after
detecting the completed transfer, and prior to
updating the contents of SSPxBUF.
Also verify that the Write Collision bit (WCOL) is
clear after writing SSPxBUF. If WCOL is set, clear
the bit in software and rewrite the contents of
SSPxBUF.
Date Codes that pertain to this issue:
All engineering and production devices.
16. Module: MSSP (I
2
C™ Mode)
In its current implementation, the I
2
C Master mode
operates as follows:
a) The Baud Rate Generator for I
2
C in Master
mode is slower than the rates specified in
Table 17-3 of the Device Data Sheet.
For this revision of silicon, use the values
shown in Table 2 (below) in place of those
shown in Table 17-3 of the Device Data Sheet.
The differences are shown in bold text.
b) Use the following formula in place of the
one shown in Register 19-4 (SSPxCON1)
of the Device Data Sheet for bit description
SSPM3:SSPM0 = 1000.
SSPxADD = INT((F
CY/FSCL) – (FCY/1.111 MHz)) – 1
Date Codes that pertain to this issue:
All engineering and production devices.
TABLE 2: I
2
C™ CLOCK RATE w/BRG
loop_MSB:
MOVF SSP1STAT, W
BTFSS WREG, BF
BRA loop_MSB
FOSC FCY FCY * 2 BRG Value
F
SCL
(2 Rollovers of BRG)
40 MHz 10 MHz 20 MHz 0Eh 400 kHz
(1)
40 MHz 10 MHz 20 MHz 15h 312.5 kHz
40 MHz 10 MHz 20 MHz 59h 100 kHz
16 MHz 4 MHz 8 MHz 05h 400 kHz
(1)
16 MHz 4 MHz 8 MHz 08h 308 kHz
16 MHz 4 MHz 8 MHz 23h 100 kHz
4 MHz 1 MHz 2 MHz 01h 333 kHz
(1)
4 MHz 1 MHz 2 MHz 08h 100 kHz
4 MHz 1 MHz 2 MHz 00h 1 MHz
(1)
Note 1: The I
2
C™ interface does not conform to the 400 kHz I
2
C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.