Datasheet

PIC18F6527/6622/8527/8622
DS80253B-page 2 © 2006 Microchip Technology Inc.
4. Module: EUSART
In 9-Bit Asynchronous Full-Duplex Receive mode,
received data may be corrupted if the TX9D bit
(TXSTAx<0>) is not modified immediately after
RCIDL (BAUDCONx<6>) is set.
Work around
Only write to TX9D when a reception is not in
progress (RCIDL = 1). No interrupt is associated
with RCIDL, therefore, it must be polled in software
to determine when TX9D can be updated.
5. Module: ECCP
PIC18F6XXX device’s Configuration Word,
CONFIG3L, is not unimplemented and will switch
the ECCP2 output pin similar to the PIC18F8XXX
devices if the Processor mode does not select
Microcontroller mode.
Work around
In MPLAB
®
IDE, program the PIC18F6XXX device
as its PIC18F8XXX equivalent and assign the
Processor mode bits (PM<1:0>) to ‘11’ for
Microcontroller mode.
6. Module: External Memory Bus
For PIC18F8XXX devices, the Stack Pointer may
incorrectly increment during a table read operation
if the external memory bus wait states are enabled
(i.e., Configuration bit, WAIT, is clear
(CONFIG3L<7> = 0) and WAIT<1:0> bits
(MEMCON<5:4>) are not equal to ‘11’).
Work around
If using the external memory bus and performing
TBLRD operations with a non-zero wait state
(CONFIG3L<7> = 0 and WAIT<1:0>
(MEMCON<5:4>) are not equal to ‘11’), disable
interrupts by clearing the GIE/GIEH (INTCON<7>)
and PEIE/GIEL (INTCON<6>) bits prior to executing
any TBLRD operation.
7. Module: MSSP
In SPI mode, the Buffer Full flag (BF bit in the
SSPxSTAT register), the Write Collision Detect bit
(WCOL bit in SSPxCON1) and the Receive
Overflow Indicator bit (SSPOV in SSPxCON1) are
not reset upon disabling the SPI module (by
clearing the SSPEN bit in the SSPxCON1
register).
For example, if SSPxBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPxBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
8. Module: Timer1
In 16-Bit Asynchronous Counter mode or 16-Bit
Asynchronous Oscillator mode, the TMR1H and
TMR3H buffers do not update when TMRxL is
read. This issue only affects reading the TMRxH
registers. The timers increment and set the inter-
rupt flags as expected. The Timer registers can
also be written as expected.
Work around
Use 8-bit mode by clearing the RD16 (T1CON<7>)
bit or use the synchronization option by clearing
T1SYNC (T1CON<2>).
9. Module: PORTE
The RE4 pin latch remains at tri-state when the
ECCPMX Configuration bit is clear and selects
PORTH.
Work around
This issue will be corrected in a future revision of
silicon.