Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 78 © 2007 Microchip Technology Inc.
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 61, 201
RCREG1 EUSART1 Receive Register 0000 0000 61, 208
TXREG1 EUSART1 Transmit Register 0000 0000 61, 206
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 61, 198
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 61, 199
IPR3
— LCDIP RC2IP TX2IP — — — — -111 ---- 61, 106
PIR3
— LCDIF RC2IF TX2IF — — — — -000 ---- 61, 100
PIE3
— LCDIE RC2IE TX2IE — — — — -000 ---- 61, 103
IPR2 OSCFIP CMIP
— — BCLIP HLVDIP TMR3IP CCP2IP 11-- 1111 61, 105
PIR2 OSCFIF CMIF
— — BCLIF HLVDIF TMR3IF CCP2IF 00-- 0000 61, 99
PIE2 OSCFIE CMIE
— — BCLIE HLVDIE TMR3IE CCP2IE 00-- 0000 61, 102
IPR1
— ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 61, 104
PIR1
— ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 61, 98
PIE1
— ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 61, 101
OSCTUNE INTSRC PLLEN
(3)
— TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 35, 61
TRISJ
(2)
PORTJ Data Direction Register 1111 1111 62, 130
TRISH
(2)
PORTH Data Direction Register 1111 1111 62, 128
TRISG
— — — PORTG Data Direction Register ---1 1111 62, 126
TRISF PORTF Data Direction Register 1111 1111 62, 124
TRISE PORTE Data Direction Register
— — — — 1111 ---- 62, 121
TRISD PORTD Data Direction Register 1111 1111 62, 119
TRISC PORTC Data Direction Register 1111 1111 62, 117
TRISB PORTB Data Direction Register 1111 1111 62, 114
TRISA TRISA7
(5)
TRISA6
(5)
PORTA Data Direction Register 1111 1111 62, 111
LATJ
(2)
LATJ Data Output Register xxxx xxxx 62, 130
LATH
(2)
LATH Data Output Register xxxx xxxx 62, 128
LATG
— — — LATG Data Output Register ---x xxxx 62, 126
LATF LATF Data Output Register xxxx xxxx 62, 124
LATE LATE Data Output Register
— — — — xxxx ---- 62, 121
LATD LATD Data Output Register xxxx xxxx 62, 119
LATC LATC Data Output Register xxxx xxxx 62, 117
LATB LATB Data Output Register xxxx xxxx 62, 114
LATA LATA7
(5)
LATA6
(5)
LATA Data Output Register xxxx xxxx 62, 111
PORTJ
(2)
Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 62, 130
PORTH
(2)
Read PORTH pins, Write PORTH Data Latch xxxx xxxx 62, 128
PORTG
— —RG5
(4)
Read PORTG pins <4:0>, Write PORTG Data Latch <4:0> --xx xxxx 62, 126
PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 62, 124
PORTE Read PORTE pins, Write PORTE Data Latch
— — — — xxxx ---- 62, 121
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 62, 119
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 62, 117
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 62, 114
PORTA RA7
(5)
RA6
(5)
Read PORTA pins, Write PORTA Data Latch xx0x 0000 62, 111
TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.