Datasheet

© 2007 Microchip Technology Inc. DS39629C-page 77
PIC18F6390/6490/8390/8490
TMR0H Timer0 Register High Byte 0000 0000 60, 132
TMR0L Timer0 Register Low Byte xxxx xxxx 60, 132
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 60, 131
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 38, 60
HLVDCON VDIRMAG
— IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 60, 251
WDTCON
— — — — — — —SWDTEN--- ---0 60, 288
RCON IPEN SBOREN
(1)
—RITO PD POR BOR 0q-1 11q0 52, 60,
107
TMR1H Timer1 Register High Byte xxxx xxxx 60, 137
TMR1L Timer1 Register Low Byte xxxx xxxx 60, 137
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 60, 135
TMR2 Timer2 Register 0000 0000 60, 141
PR2 Timer2 Period Register 1111 1111 60, 141
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 60, 141
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 60, 158,
166
SSPADD MSSP Address Register in I
2
C™ Slave Mode. MSSP Baud Rate Reload Register in I
2
C Master Mode. 0000 0000 60, 166
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 60, 158,
167
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 60, 159,
168
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 60, 169
ADRESH A/D Result Register High Byte xxxx xxxx 61, 240
ADRESL A/D Result Register Low Byte xxxx xxxx 61, 240
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 61, 231
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 61, 232
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 61, 233
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 61, 152,
155
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 61, 152,
155
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 61, 147
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 61, 152,
155
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 61, 152,
155
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 61, 147
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 61, 247
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 61, 241
TMR3H Timer3 Register High Byte xxxx xxxx 61, 145
TMR3L Timer3 Register Low Byte xxxx xxxx 61, 145
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 61, 143
TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.