Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 264 © 2007 Microchip Technology Inc.
22.6 Pixel Control
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Table 22-2 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any LCD pixel location not being used for display can
be used as general purpose RAM.
22.7 LCD Frame Frequency
The rate at which the COM and SEG outputs changes
is called the LCD frame frequency
TABLE 22-4: FRAME FREQUENCY
FORMULAS
TABLE 22-5: APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
F
OSC @ 32 MHz,
TIMER1 @ 32.768 kHz OR
INTRC OSCILLATOR
22.8 LCD Waveform Generation
LCD waveform generation is based on the philosophy
that the net AC voltage across the dark pixel should be
maximized and the net AC voltage across the clear
pixel should be minimized. The net DC voltage across
any pixel should be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
The pixel signal (COM-SEG) will have no DC com-
ponent and it can take only one of the two rms values.
The higher rms value will create a dark pixel and a
lower rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In Type-A waveform, the phase
changes within each common type, whereas in Type-B
waveform, the phase changes on each frame
boundary. Thus, Type-A waveform maintains 0 V
DC
over a single frame, whereas Type-B waveform takes
two frames.
Figure 22-4 through Figure 22-14 provide waveforms
for static, half-multiplex, one-third-multiplex and
quarter-multiplex drives for Type-A and Type-B
waveforms.
Multiplex Frame Frequency =
Static Clock Source/(4 x 1 x (LP3:LP0 + 1))
1/2 Clock Source/(2 x 2 x (LP3:LP0 + 1))
1/3 Clock Source/(1 x 3 x (LP3:LP0 + 1))
1/4 Clock Source/(1 x 4 x (LP3:LP0 + 1))
Note: Clock source is (F
OSC/4)/8192,
Timer1 Osc/32 or INTRC/32.
LP3:LP0 Static 1/2 1/3 1/4
1 125 125 167 125
2838311183
3 62 628362
4 50 506750
5 42 425642
6 36 364836
7 31 314231
Note 1: If Sleep has to be executed with LCD
Sleep enabled (LCDCON<SLPEN> is
‘1’), then care must be taken to execute
Sleep only when V
DC on all the pixels is
‘0’.
2: When the LCD clock source is
(F
OSC/4)/8192, if Sleep is executed
irrespective of the LCDCON<SLPEN>
setting, the LCD goes into Sleep. Thus,
take care to see that V
DC on all pixels is ‘0’
when Sleep is executed.