Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 258 © 2007 Microchip Technology Inc.
22.1 LCD Registers
The LCD driver module has 32 registers:
• LCD Control Register (LCDCON)
• LCD Phase Register (LCDPS)
• Six LCD Segment Enable Registers
(LCDSE5:LCDSE0)
• 24 LCD Data Registers
(LCDDATA23:LCDDATA0)
The LCDCON register, shown in Register 22-1,
controls the overall operation of the module. Once the
module is configured, the LCDEN (LCDCON<7>) bit is
used to enable or disable the LCD module. The LCD
panel can also operate during Sleep by clearing the
SLPEN (LCDCON<6>) bit.
The LCDPS register, shown in Register 22-2,
configures the LCD clock source prescaler and the type
of waveform, Type-A or Type-B. Details on these
features are provided in Section 22.2 “LCD Clock
Source Selection”, Section 22.3 “LCD Bias Types”
and Section 22.8 “LCD Waveform Generation”.
REGISTER 22-1: LCDCON: LCD CONTROL REGISTER
R/W-0 R/W-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0
bit 7 bit 0
Legend: C = Clearable Only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 LCDEN: LCD Driver Enable bit
1 = LCD driver module is enabled
0 = LCD driver module is disabled
bit 6 SLPEN: LCD Driver Enable in Sleep mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
bit 5 WERR: LCD Write Failed Error bit
1 = LCDDATAx register written while LCDPS<WA> = 0 (must be cleared in software)
0 = No LCD write error
bit 4 Unimplemented: Read as ‘0’
bit 3-2 CS1:CS0: Clock Source Select bits
00 = (F
OSC/4)/8192
01 = T13CKI (Timer1)/32
1x = INTRC (31.25 kHz)/32
bit 1-0 LMUX1:LMUX0: Commons Select bits
LMUX1:LMUX0 Multiplex
Maximum
Number of
Pixels
(PIC18F6X90)
Maximum
Number of
Pixels
(PIC18F8X90)
Bias
00 Static (COM0) 32 48 Static
01 1/2 (COM1:COM0) 64 96 1/2 or 1/3
10 1/3 (COM2:COM0) 96 144 1/2 or 1/3
11 1/4 (COM3:COM0) 128 192 1/3