Datasheet

© 2007 Microchip Technology Inc. DS39629C-page 225
PIC18F6390/6490/8390/8490
FIGURE 17-5: ASYNCHRONOUS RECEPTION
TABLE 17-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1bit 0 bit 7/8
bit 0Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX2 (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG2
Word 2
RCREG2
Stop
bit
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third
word causing the OERR (Overrun) bit to be set.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59
PIR3 — LCDIF RC2IF TX2IF — — — —61
PIE3 — LCDIE RC2IE TX2IE — — — —61
IPR3
— LCDIP RC2IP TX2IP — — — —61
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63
RCREG2 AUSART2 Receive Register 63
TXSTA2
CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 63
SPBRG2 AUSART2 Baud Rate Generator Register 63
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.