Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 110 © 2007 Microchip Technology Inc.
TABLE 9-1: PORTA FUNCTIONS
Pin Name Function
TRIS
Setting
I/O Buffer Description
RA0/AN0 RA0 0 O DIG LATA<0> data output. Not affected by analog pin setting.
1 I TTL PORTA<0> data input. Reads ‘0’ on POR.
AN0 1 I ANA A/D input channel 0. Default configuration on POR.
RA1/AN1 RA1 0 O DIG LATA<1> data output. Not affected by analog pin setting.
1 I TTL PORTA<1> data input. Reads ‘0’ on POR.
AN1 1 I ANA A/D input channel 1. Default configuration on POR.
RA2/AN2/V
REF-/
SEG16
RA2 0 O DIG LATA<2> data output. Not affected by analog pin setting; disabled
when LCD segment enabled.
1 I TTL PORTA<2> data input. Reads ‘0’ on POR.
AN2 1 I ANA A/D input channel 2. Default configuration on POR.
V
REF- 1 I ANA A/D low reference voltage input.
SEG16 x O ANA Segment 16 analog output for LCD.
RA3/AN3/V
REF+/
SEG17
RA3 0 O DIG LATA<3> data output. Output is unaffected by analog pin setting;
disabled when LCD segment enabled.
1 I TTL PORTA<3> data input. Reads ‘0’ on POR.
AN3 1 I ANA A/D input channel 3. Default configuration on POR.
V
REF+ 1 I ANA A/D high reference voltage input.
SEG17 x O ANA Segment 17 analog output for LCD. Disables all other digital outputs.
RA4/T0CKI/
SEG14
RA4 0 O DIG LATA<4> data output; disabled when LCD segment enabled.
1 I ST PORTA<4> data input.
T0CKI I ST Timer0 clock input.
SEG14 x O ANA Segment 14 analog output for LCD.
RA5/AN4/
HLVDIN/SEG15
RA5 0 O DIG LATA<5> data output. Not affected by analog pin setting; disabled
when LCD segment enabled.
1 I TTL PORTA<5> data input. Reads ‘0’ on POR.
AN4 1 I ANA A/D input channel 5. Default configuration on POR.
HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input.
SEG15 x O ANA Segment 15 analog output for LCD.
OSC2/CLKO/RA6
OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes).
CLKO x O DIG System cycle clock output (F
OSC/4) in all oscillator modes except
RCIO, INTIO2 and ECIO.
RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
OSC1/CLKI/RA7
OSC1 x I ANA Main oscillator input connection, all modes except INTIO.
CLKI x I ANA Main clock input connection, all modes except INTIO.
RA7 0 O DIG LATA<7> data output. Available only in INTIO modes; otherwise reads
as ‘0’.
1 I TTL PORTA<7> data input. Available only in INTIO modes; otherwise reads
as ‘0’.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).