Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 82  2010 Microchip Technology Inc.
SPBRGH1 EUSART1 Baud Rate Generator High Byte 0000 0000 66, 221
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00 66, 220
SPBRG2 AUSART2 Baud Rate Generator 0000 0000 66, 234
RCREG2 AUSART2 Receive Register 0000 0000 66, 248
TXREG2 AUSART2 Transmit Register xxxx xxxx 66, 246
TXSTA2 CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 66, 242
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 66, 243
TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in
INTOSC Modes”.
4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: STKFUL and STKUNF bits are cleared by user software or by a POR.