Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 80  2010 Microchip Technology Inc.
TMR0H Timer0 Register High Byte 0000 0000 64, 153
TMR0L Timer0 Register Low Byte xxxx xxxx 64, 153
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 64, 151
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 42, 64
HLVDCON VDIRMAG
— IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 64, 275
WDTCON
— — — — — — —SWDTEN---- ---0 64, 291
RCON IPEN SBOREN
(1)
—RITO PD POR BOR 0q-1 11q0 56, 64,
123
TMR1H Timer1 Register High Byte xxxx xxxx 64, 159
TMR1L Timer1 Register Low Byte 0000 0000 64, 159
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 64, 155
TMR2 Timer2 Register 1111 1111 64, 162
PR2 Timer2 Period Register -000 0000 64, 162
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 64, 161
SSPBUF MSSP Receive Buffer/Transmit Register 0000 0000 64, 178,
186
SSPADD MSSP Address Register in I
2
C™ Slave Mode. MSSP Baud Rate Reload Register in I
2
C Master Mode. 0000 0000 64, 186
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 64, 178,
188
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 64, 179,
179
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 64, 189
ADRESH A/D Result Register High Byte xxxx xxxx 64, 264
ADRESL A/D Result Register Low Byte 0000 0000 64, 264
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 64, 255
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 qqqq 64, 256
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 64, 257
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 65, 168
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 65, 168
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 65, 167
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 65, 168
CCPR2L Capture/Compare/PWM Register 2 Low Byte 0000 0000 65, 168
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 65, 167
CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 65, 168
CCPR3L Capture/Compare/PWM Register 3 Low Byte 0000 0000 65, 168
CCP3CON
— — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 65, 167
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 65, 271
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 65, 265
TMR3H Timer3 Register High Byte 0000 0000 65, 163
TMR3L Timer3 Register Low Byte 0000 0000 65, 165
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 65, 163
PSPCON IBF OBF IBOV PSPMODE
— — — — 0000 ---- 65, 149
TABLE 6-3: REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in
INTOSC Modes”.
4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: STKFUL and STKUNF bits are cleared by user software or by a POR.