Datasheet

PIC18F6310/6410/8310/8410
DS39635C-page 54  2010 Microchip Technology Inc.
TABLE 4-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
Before Wake-up
Clock Source
After Wake-up
Exit Delay
Clock Ready Status Bit
(OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
T
CSD
(2)
OSTS
HSPLL
EC, RC, INTRC
(1)
—
INTOSC
(3)
IOFS
T1OSC or INTRC
(1)
LP, XT, HS TOST
(4)
OSTS
HSPLL T
OST + t
rc
(4)
EC, RC, INTRC
(1)
TCSD
(2)
—
INTOSC
(2)
TIOBST
(5)
IOFS
INTOSC
(3)
LP, XT, HS TOST
(5)
OSTS
HSPLL T
OST + t
rc
(4)
EC, RC, INTRC
(1)
TCSD
(2)
—
INTOSC
(2)
None IOFS
None
(Sleep mode)
LP, XT, HS TOST
(4)
OSTS
HSPLL T
OST + t
rc
(4)
EC, RC, INTRC
(1)
TCSD
(2)
—
INTOSC
(2)
TIOBST
(5)
IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (Parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 4.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: T
OST is the Oscillator Start-up Timer (Parameter 32). t
rc
is the PLL Lock-out Timer (Parameter F12); it is
also designated as T
PLL.
5: Execution continues during TIOBST (Parameter 39), the INTOSC stabilization period.