Datasheet

 2010 Microchip Technology Inc. DS39635C-page 407
PIC18F6310/6410/8310/8410
Timer0 .............................................................................. 151
16-Bit Mode Timer Reads and Writes ...................... 152
Associated Registers ............................................... 153
Clock Source Edge Select (T0SE Bit) ...................... 152
Clock Source Select (T0CS Bit) ............................... 152
Operation ................................................................. 152
Overflow Interrupt .................................................... 153
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 155
16-Bit Read/Write Mode ........................................... 157
Associated Registers ............................................... 159
Interrupt .................................................................... 158
Low-Power Option ................................................... 157
Operation ................................................................. 156
Oscillator .......................................................... 155, 157
Oscillator Layout Considerations ............................. 158
Overflow Interrupt .................................................... 155
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 158
TMR1H Register ...................................................... 155
TMR1L Register ....................................................... 155
Use as a Real-Time Clock ....................................... 158
Using as a Clock Source .......................................... 157
Timer2 .............................................................................. 161
Associated Registers ............................................... 162
Interrupt .................................................................... 162
Operation ................................................................. 161
Output ...................................................................... 162
PR2 Register ............................................................ 173
TMR2 to PR2 Match Interrupt .................................. 173
Timer3 .............................................................................. 163
16-Bit Read/Write Mode ........................................... 165
Associated Registers ............................................... 165
Operation ................................................................. 164
Oscillator .......................................................... 163, 165
Overflow Interrupt ............................................ 163, 165
Special Event Trigger (CCP) .................................... 165
TMR3H Register ...................................................... 163
TMR3L Register ....................................................... 163
Timing Diagrams
A/D Conversion ........................................................ 388
Acknowledge Sequence .......................................... 210
Asynchronous Reception ................................. 230, 249
Asynchronous Transmission ............................ 227, 247
Asynchronous Transmission
(Back to Back) ......................................... 227, 247
Automatic Baud Rate Calculation ............................ 225
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 233
Auto-Wake-up Bit (WUE) During Sleep ................... 233
Baud Rate Generator with Clock Arbitration ............ 204
BRG Overflow Sequence ......................................... 225
BRG Reset Due to SDA Arbitration During
Start Condition ................................................. 213
Brown-out Reset (BOR) ........................................... 375
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 214
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 214
Bus Collision During a Start
Condition (SCL = 0) ......................................... 213
Bus Collision During a Start
Condition (SDA Only) ...................................... 212
Bus Collision During a Stop Condition (Case 1) ...... 215
Bus Collision During a Stop Condition (Case 2) ...... 215
Bus Collision for Transmit and Acknowledge .......... 211
Capture/Compare/PWM (All CCP Modules) ............ 377
CLKO and I/O .......................................................... 372
Clock Synchronization ............................................. 197
Clock/Instruction Cycle .............................................. 73
Example SPI Master Mode (CKE = 0) ..................... 378
Example SPI Master Mode (CKE = 1) ..................... 379
Example SPI Slave Mode (CKE = 0) ....................... 380
Example SPI Slave Mode (CKE = 1) ....................... 381
External Clock (All Modes Except PLL) ................... 370
External Memory Bus for SLEEP (16-Bit
Microprocessor Mode) ..................................... 101
External Memory Bus for SLEEP (8-Bit
Microprocessor Mode) ..................................... 104
External Memory Bus for TBLRD (16-Bit
Extended Microcontroller Mode) ...................... 100
External Memory Bus for TBLRD (16-Bit
Microprocessor Mode) ..................................... 100
External Memory Bus for TBLRD (8-Bit
Extended Microcontroller Mode) ...................... 103
External Memory Bus for TBLRD (8-Bit
Microprocessor Mode) ..................................... 103
Fail-Safe Clock Monitor ........................................... 294
High/Low-Voltage Detect (VDIRMAG = 1) ............... 278
High/Low-Voltage Detect Characteristics ................ 367
High/Low-Voltage Detect Operation
(VDIRMAG = 0) ............................................... 277
I
2
C Bus Data ............................................................ 382
I
2
C Bus Start/Stop Bits ............................................ 382
I
2
C Master Mode (7 or 10-Bit Transmission) ........... 208
I
2
C Master Mode (7-Bit Reception) ......................... 209
I
2
C Master Mode First Start Bit ................................ 205
I
2
C Slave Mode (10-Bit Reception, SEN = 0) .......... 194
I
2
C Slave Mode (10-Bit Reception, SEN = 1) .......... 199
I
2
C Slave Mode (10-Bit Transmission) .................... 195
I
2
C Slave Mode (7-bit Reception, SEN = 0) ............ 192
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............ 198
I
2
C Slave Mode (7-Bit Transmission) ...................... 193
I
2
C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 200
I
2
C Stop Condition Receive or Transmit Mode ........ 210
Master SSP I
2
C Bus Data ....................................... 384
Master SSP I
2
C Bus Start/Stop Bits ........................ 384
Parallel Slave Port (PSP) Read ............................... 150
Parallel Slave Port (PSP) Write ............................... 149
Program Memory Read ........................................... 373
Program Memory Write ........................................... 374
PWM Output ............................................................ 173
Repeated Start Condition ........................................ 206
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 375
Send Break Character Sequence ............................ 234
Slave Synchronization ............................................. 183
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT) ............................................ 61
SPI Mode (Master Mode) ........................................ 182
SPI Mode (Slave Mode, CKE = 0) ........................... 184
SPI Mode (Slave Mode, CKE = 1) ........................... 184
Synchronous Reception (Master Mode,
SREN) ..................................................... 237, 252
Synchronous Transmission ............................. 235, 250
Synchronous Transmission
(Through TXEN) ...................................... 236, 251
Time-out Sequence on POR w/PLL Enabled
(MCLR
Tied to VDD) .......................................... 61