Datasheet

 2010 Microchip Technology Inc. DS39635C-page 37
PIC18F6310/6410/8310/8410
3.4 RC Oscillator
For timing-insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The actual oscillator frequency is a function of several
factors:
• Supply voltage
• Values of the external resistor (R
EXT) and
capacitor (C
EXT)
• Operating temperature
Given the same device, operating voltage and
temperature and component values, there will also be
unit-to-unit frequency variations. These are due to
factors such as:
• Normal manufacturing variation
• Difference in lead frame capacitance between
package types (especially for low C
EXT values)
• Variations within the tolerance of limits of REXT
and C
EXT
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows how the R/C combination is
connected.
FIGURE 3-5: RC OSCILLATOR MODE
The RCIO Oscillator mode (Figure 3-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 3-6: RCIO OSCILLATOR MODE
3.5 PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
3.5.1 HSPLL OSCILLATOR MODE
The HSPLL mode makes use of the HS Oscillator
mode for frequencies up to 10 MHz. A PLL then
multiplies the oscillator output frequency by 4 to
produce an internal clock frequency up to 40 MHz.
The PLL is only available to the crystal oscillator when
the FOSC<3:0> Configuration bits are programmed for
HSPLL mode (= 0110).
FIGURE 3-7: PLL BLOCK DIAGRAM
(HS MODE)
3.5.2 PLL AND INTOSC
The PLL is also available to the internal oscillator block
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock out-
put of up to 32 MHz. The operation of INTOSC with the
PLL is described in Section 3.6.4 “PLL in INTOSC
Modes”.
OSC2/CLKO
CEXT
REXT
PIC18FXXXX
OSC1
F
OSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 k  REXT  100 k
C
EXT > 20 pF
CEXT
REXT
PIC18FXXXX
OSC1
Internal
Clock
VDD
VSS
Recommended values: 3 k  REXT  100 k
C
EXT > 20 pF
I/O (OSC2)
RA6
MUX
VCO
Loop
Filter
Crystal
Oscillator
OSC2
OSC1
PLL Enable
F
IN
FOUT
SYSCLK
Phase
Comparator
HS Oscillator Enable
4
(from Configuration Register 1H)
HS Mode